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At least 145 records · Page 8

All sources NASA NTRS DOE OSTI

NASA NTRS2022

Space Induced Discharge Model to Be Used on Interface Circuit Vulnerability Assessment

Charging can occur in space due to plasma and high energy particles. Charging is especially severe in certain earth orbits such as geostationary orbit, medium earth orbit and highly inclined orbit. A spacecraft that travels to other planets such as Jupiter also encounters high level of charging due to Jupiter’s radiation belt. The major concern for spacecraft operation due to charging is the survival of sensitive electrical circuits. Dielectrics and floating metal can charge up and discharge onto interface circuits. The electrical circuits need to be evaluated for survival from the electrostatic-discharge (ESD) threat. Both ESD induced upset and damage need to be assessed. The interface circuits are often located inside a shielded unit in the spacecraft structure or a shielded vault with sufficient radiation shielding to avoid surface and internal charging. The materials external to the highly shielded area can charge up and discharge onto wires that can directly dissipate the ESD onto the interface circuits. Figure 1 shows a possible discharge mechanism onto the interfacing circuits. If the wire has an external shield or a coaxial line, some or most of the discharge can flow on the shield to chassis ground. There is always coupling from external discharge. If the wire has no shield, the discharge flows onto the interface circuit. Fig. 1 Possible discharge paths onto the interface circuits. The purpose of this article is to address how to model the ESD threat to be used as the discharge source onto the interface circuit based on the electron beam test data. Different models are needed for different impedances associated with the interface circuits. Once those models are derived, one needs to analyze the interface circuit with the corresponding model using an electrical simulation tool. Then, the circuit’s front-end components can be assessed for damage and upset. Upset is highly dependent on the circuit operation and system requirements, and thus it is not addressed any further. Damage of electrical parts is often rated under Human-Body-Model (HBM) ESD. One can utilize this industry-wide available information to assess the damage vulnerability due to space discharges. However, the HBM waveform does not always match the discharge waveform. To estimate the damage vulnerability of the circuit and set margin, one needs to compare the equivalent energy delivered to the victim between a HBM discharge and the results from an ESD source model based on actual discharges. This paper presents such a comparison for a few select cases.

Xie, Julie↗

DOE OSTI2011

Recycling of WEEE: Characterization of spent printed circuit boards from mobile phones and computers

Highlights: > This paper presents new and important data on characterization of wastes of electric and electronic equipments. > Copper concentration is increasing in mobile phones and remaining constant in personal computers. > Printed circuit boards from mobile phones and computers would not be mixed prior treatment. - Abstract: This paper presents a comparison between printed circuit boards from computers and mobile phones. Since printed circuits boards are becoming more complex and smaller, the amount of materials is constantly changing. The main objective of this work was to characterize spent printed circuit boards from computers and mobile phones applying mineral processing technique to separate the metal, ceramic, and polymer fractions. The processing was performed by comminution in a hammer mill, followed by particle size analysis, and by magnetic and electrostatic separation. Aqua regia leaching, loss-on-ignition and chemical analysis (inductively coupled plasma atomic emission spectroscopy - ICP-OES) were carried out to determine the composition of printed circuit boards and the metal rich fraction. The composition of the studied mobile phones printed circuit boards (PCB-MP) was 63 wt.% metals; 24 wt.% ceramics and 13 wt.% polymers; and of the printed circuit boards from studied personal computers (PCB-PC) was 45 wt.% metals; 27 wt.% polymers and ceramics 28 wt.% ceramics. The chemical analysis showed that copper concentration in printed circuit boards from personal computers was 20 wt.% and in printed circuit boards from mobile phones was 34.5 wt.%. According to the characteristics of each type of printed circuit board, the recovery of precious metals may be the main goal of the recycling process of printed circuit boards from personal computers and the recovery of copper should be the main goal of the recycling process of printed circuit boards from mobile phones. Hence, these printed circuit boards would not be mixed prior treatment. The results of this paper show that copper concentration is increasing in mobile phones and remaining constant in personal computers.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

NASA NTRS1973

Phase control circuits using frequency multiplications for phased array antennas

A phase control coupling circuit for use with a phased array antenna is described. The coupling circuit includes a combining circuit which is coupled to a transmission line, a frequency multiplier circuit which is coupled to the combining circuit, and a recombining circuit which is coupled between the frequency multiplier circuit and phased array antenna elements. In a doubler embodiment, the frequency multiplier circuit comprises frequency doublers and the combining and recombining circuits comprise four-port hybrid power dividers. In a generalized embodiment, the multiplier circuit comprises frequency multiplier elements which multiply to the Nth power, the combining circuit comprises four-part hybrid power dividers, and the recombinding circuit comprises summing circuits.

Mailloux, R. J.↗

NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗

DOE OSTI2017

Design and Characterization of DNA Strand-Displacement Circuits in Serum-Supplemented Cell Medium

The functional stability and lifetimes of synthetic molecular circuits in biological environments are important for long-term, stable sensors or controllers of cell or tissue behavior. DNA-based molecular circuits, particularly DNA strand-displacement circuits, provide simple and effective biocompatible control mechanisms and sensors, but are vulnerable to digestion by nucleases present in living tissues and serum-supplemented cell culture. The stability of double-stranded and single-stranded DNA circuit components in serum-supplemented cell medium and the corresponding effect of nuclease-mediated degradation on circuit performance were characterized to determine the major routes of degradation and DNA strand-displacement circuit failure. Simple circuit design choices, such as the use of 5' toeholds within the DNA complexes used as reactants in the strand-displacement reactions and the termination of single-stranded components with DNA hairpin domains at the 3' termini, significantly increase the functional lifetime of the circuit components in the presence of nucleases. Furthermore, simulations of multireaction circuits, guided by the experimentally measured operation of single-reaction circuits, enable predictive realization of multilayer and competitive-reaction circuit behavior. Altogether, these results provide a basic route to increased DNA circuit stability in cell culture environments.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2021

Quantum circuit cutting with maximum-likelihood tomography

Abstract We introduce maximum-likelihood fragment tomography (MLFT) as an improved circuit cutting technique for running clustered quantum circuits on quantum devices with a limited number of qubits. In addition to minimizing the classical computing overhead of circuit cutting methods, MLFT finds the most likely probability distribution for the output of a quantum circuit, given the measurement data obtained from the circuit’s fragments. We demonstrate the benefits of MLFT for accurately estimating the output of a fragmented quantum circuit with numerical experiments on random unitary circuits. Finally, we show that circuit cutting can estimate the output of a clustered circuit with higher fidelity than full circuit execution, thereby motivating the use of circuit cutting as a standard tool for running clustered circuits on quantum hardware.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1994

Novel high-gain, improved-bandwidth, finned-ladder V-band Traveling-Wave Tube slow-wave circuit design

The V-band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for inter-satellite communications. As a first effort to develop a high-efficiency V-band Traveling-Wave Tube (TWT), variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite these advantages, however, low bandwidth and high voltage requirements have, until now, prevented its acceptance outside the laboratory. In this paper, the three-dimensional electrodynamic simulation code MAFIA (solution of MAxwell's Equation by the Finite-Integration-Algorithm) is used to investigate methods of increasing the bandwidth and lowering the operating voltage of the ring-plane circuit. Calculations of frequency-phase dispersion, beam on-axis interaction impedance, attenuation and small-signal gain per wavelength were performed for various geometric variations and loading distributions of the ring-plane TWT slow-wave circuit. Based on the results of the variations, a circuit termed the finned-ladder TWT slow-wave circuit was designed and is compared here to the scaled prototype ring-plane and a conventional ferruled coupled-cavity TWT circuit over the V-band frequency range. The simulation results indicate that this circuit has a much higher gain, significantly wider bandwidth, and a much lower voltage requirement than the scaled ring-plane prototype circuit, while retaining its excellent thermal dissipation properties. The finned-ladder circuit has a much larger small-signal gain per wavelength than the ferruled coupled-cavity circuit, but with a moderate sacrifice in bandwidth.

Kory, Carol L.↗

DOE OSTI2015

Approximate circuits for increased reliability

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

42 ENGINEERING↗

DOE OSTI2015

Approximate circuits for increased reliability

42 ENGINEERING↗

DOE OSTI2025

Circuit complexity and functionality: A statistical thermodynamics perspective

Circuit complexity, defined as the minimum circuit size required for implementing a particular Boolean computation, is a foundational concept in computer science. Determining circuit complexity is believed to be a hard computational problem. Recently, in the context of black holes, circuit complexity has been promoted to a physical property, wherein the growth of complexity is reflected in the time evolution of the Einstein-Rosen bridge (“wormhole”) connecting the two sides of an anti-de Sitter “eternal” black hole. Here, we are motivated by an independent set of considerations and explore links between complexity and thermodynamics for functionally equivalent circuits, making the physics-inspired approach relevant to real computational problems, for which functionality is the key element of interest. In particular, our thermodynamic framework provides an alternative perspective on the obfuscation of programs of arbitrary length—an important problem in cryptography—as thermalization through recursive mixing of neighboring sections of a circuit, which can be viewed as the mixing of two containers with “gases of gates.” This recursive process equilibrates the average complexity and leads to the saturation of the circuit entropy, while preserving functionality of the overall circuit. The thermodynamic arguments hinge on ergodicity in the space of circuits which we conjecture is limited to disconnected ergodic sectors due to fragmentation. The notion of fragmentation has important implications for the problem of circuit obfuscation as it implies that there are circuits of same size and functionality that cannot be connected via a polynomial number of local moves. Furthermore, we argue that fragmentation is unavoidable unless the complexity classes NP and coNP coincide, a statement that implies the collapse of the polynomial hierarchy of computational complexity theory to its first level.

Science & Technology - Other Topics↗

DOE OSTI2015

Distribution System Secondary Circuit Parameter Estimation for Model Calibration

To analyze and coordinate the operation of distribution systems with rapidly increasing amounts of PV, more accurate distribution system models are required, especially for the distribution system secondary (low-voltage) circuits down to the point of common coupling for distributed PV. There is a growing need for automated procedures to calibrate the distribution system secondary circuit models that are typically either not modeled at all or are modeled with a lower level of detail than the better modeled medium-voltage systems. This report presents an accurate, flexible, and computationally efficient method to use measurement data to estimate secondary circuit series impedance parameters in existing utility feeder models. The parameter estimation method assumes well-modeled primary circuit models, known secondary circuit topologies, and AMI active power, and reactive power measurements at all the loads in the secondary circuit. The method also requires AMI voltage measurement at most of the loads in the secondary circuit but can handle loads that do not have voltage measurements. No existing secondary circuit model information is needed, except for topology. The method is based on the well-known linearized voltage drop approximation and linear regression. The performance of the method is demonstrated on a three-phase test circuit with ten different secondary circuit topologies and on the Georgia Tech campus distribution system with AMI data. The developed method can be utilized to improve existing utility feeder models for more accurate analysis and operation with ubiquitous distributed PV interconnected on the low-voltage circuits.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗

NASA NTRS2005

Faster Evolution of More Multifunctional Logic Circuits

A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.

Stoica, Adrian↗

DOE OSTI2023

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Optically controllable molecular logic circuits

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2018

Short-Circuit Characterization and Protection of 10-kV SiC mosfet

This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. Here, a thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

10-kV SiC mosfet↗

NASA NTRS1983

Source circuit design considerations

The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.

Noel, G. T.↗

NASA NTRS1995

Electrical short circuit and current overload tests on aircraft wiring

The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

Cahill, Patricia↗