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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Lab on a Chip Application Development for Exploration

At Marshall Space Flight Center a new capability has been established to aid the advancement of microfluidics for space flight monitoring systems. Lab-On-a-Chip Application Development (LOCAD) team has created a program for advancing Technology Readiness Levels (TRL) of 1 & 2 to TRL 6 and 7, quickly and economically for Lab-On-a-Chip (LOC) applications. Scientists and engineers can utilize LOCAD's process to efficiently learn about microfluidics and determine if microfluidics is applicable to their needs. Once the applicability has been determined, LOCAD can then perform tests to develop the new fluidic protocols which are different from macro-scale chemical reaction protocols. With this information new micro-devices can be created such as the development of a microfluidic system to aid in the search for life, past and present, on Mars. Particular indicators in the Martian soil can contain the direct evidence of life. But to extract the information from the soil and present it to the proper detectors requires multiple fluidic/chemical operations. This is where LOCAD is providing its unique abilities.

Monaco, Lisa↗
NASA NTRS2004

Lab-On-a-Chip Application Development (LOCAD): Bridging Technology Readiness for Exploration

At Marshall Space Flight Center we have established a capability to investigate the use of microfluidics for space flight. The Lab-On-a-Chip Application Development (LOCAD) team has created a program for advancing Technology Readiness Levels (TRL) of 1 and 2 to TRL 6 and 7, quickly and economically for Lab-On-a-Chip (LOC) applications. Scientists and engineers can utilize LOCAD'S process to efficiently learn about microfluidics and determine if microfluidics is applicable to their needs. Once the applicability has been determined, LOCAD can then perform tests to develop the new fluidic protocols which are different from macro-scale chemical reaction protocols. With this information new micro-fluidic devices can be created and tested. Currently, LOCAD is focused on using microfluidics for both Environmental Monitoring & Control, and Medical Systems. Eventually, handheld portable units utilizing LOC technology will perform rapid tests to determine water quality, and microbial contamination levels. Since LOC technology is drastically reduced in physical size, it thereby reduces power, weight, volume, and sample requirements, a big advantage considering the resource constraints associated with spaceflight. Another one of LOCAD's current activities is the development of a microfluidic system to aid in the search for life on Mars.

Spearing, Scott F.↗
NASA NTRS1996

Radiation Behavior of Analog Neural Network Chip

A neural network experiment conducted for the Space Technology Research Vehicle (STRV-1) 1-b launched in June 1994. Identical sets of analog feed-forward neural network chips was used to study and compare the effects of space and ground radiation on the chips. Three failure mechanisms are noted.

neural networks radiation hardening graceful degra↗
NASA NTRS1995

Gas Sensor Test Chip

A new test chip is being developed to characterize conducting polymers used in gas sensors. The chip, a seven-layer cofired alumina substrate with gold electrodes, contains 11 comb and U- bend test structures. These structures are designed to measure the sheet resistance, conduction anisotropy, and peripheral conduction of spin-coated films that are not subsequently patterned.

conducting polymers gas sensors test chipnd periph↗
NASA NTRS2004

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

flight computers↗
NASA NTRS2006

A 260-340 GHz Dual Chip Frequency Tripler for THz Frequency Multiplier Chains

We designed and fabricated a fix-tuned balanced frequency tripler working in the 260-340 GHz band to be the first stage of a x3x3x3 multiplier chain to 2.7 THz. The design of a dual-chip version of this multiplier featuring an input splitter / output combiner as part of the input / output matching networks of both chips - with no degradation of the expected bandwidth and efficiency- will be presented.

Schottky diodes↗
NASA NTRS1999

Chip connectivity verification program

A method for testing electrical connectivity between conductive structures on a chip that is preferably layered with conductive and nonconductive layers. The method includes determining the layer on which each structure is located and defining the perimeter of each structure. Conductive layer connections between each of the layers are determined, and, for each structure, the points of intersection between the perimeter of that structure and the perimeter of each other structure on the chip are also determined. Finally, electrical connections between the structures are determined using the points of intersection and the conductive layer connections.

Riley, Josh↗
NASA NTRS2002

CMOS foveal image sensor chip

A foveal image sensor integrated circuit comprising a plurality of CMOS active pixel sensors arranged both within and about a central fovea region of the chip. The pixels in the central fovea region have a smaller size than the pixels arranged in peripheral rings about the central region. A new photocharge normalization scheme and associated circuitry normalizes the output signals from the different size pixels in the array. The pixels are assembled into a multi-resolution rectilinear foveal image sensor chip using a novel access scheme to reduce the number of analog RAM cells needed. Localized spatial resolution declines monotonically with offset from the imager's optical axis, analogous to biological foveal vision.

Bandera, Cesar↗
NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗
NASA NTRS2011

Characterization of 720 and 940 MHz Oscillators with Chip Antenna for Wireless Sensors from Room Temperature to 200 and 250 deg C

Oscillators that operate at 720 and 940 MHz and characterized over a temperature range of 25 C to 200 C and 250 C, respectively, are presented. The oscillators are designed on alumina substrates with typical integrated circuit fabrication techniques. Cree SiC MESFETs, thin film metal-insulator-metal capacitors and spiral inductors, and Johanson miniature chip antennas make-up the circuits. The output power and phase noise are presented as a function of temperature and frequency. Index Terms MESFETS, chip antennas, oscillators SiC alumina.

Scardelletti, Maximilian C.↗
NASA NTRS2017

Kinetics of Moisture Sorption and Reverse Bias Degradation in Chip Tantalum Capacitors

Exposure of chip MnO2 tantalum capacitors to humid environments might result in increased ESR, leakage currents, and first turn-on failures. However, there is a lack of literature data on the effect of moisture on reverse bias behavior of the parts. The presence of moisture can also result in pop-corning when a high water vapor pressure develops when moisture absorbed in pores of tantalum slugs vaporizes instantly during soldering process resulting in damage to capacitors. A study of kinetics of moisture ingress to and release from active elements of capacitors would allow a better understanding of degradation mechanisms and is important for preventing failures. In this work, a technique for investigation of moisture sorption and desorption in solid chip tantalum capacitors that employs tantalum slugs as a humidity sensor have been developed and kinetics of the process analyzed for different types of capacitors at temperatures from room to 125 ºC. A model that relates diffusion characteristics of polymer cases and size of the slugs to characteristic times of moisture sorption has been developed. A strong effect of moisture on long-term degradation of reverse bias currents in MnO2 cathode capacitors has been demonstrated and physical mechanisms discussed.

Teverovsky, Alexander↗
NASA NTRS2017

Kinetics of Moisture Sorption and Reverse Bias Degradation in Chip Tantalum Capacitors

Exposure of chip MnO2 tantalum capacitors to humid environments might result in increased ESR, leakage currents, and first turn-on failures. However, there is a lack of literature data on the effect of moisture on reverse bias behavior of the parts. The presence of moisture can also result in pop-corning when a high water vapor pressure develops when moisture absorbed in pores of tantalum slugs vaporizes instantly during soldering process resulting in damage to capacitors. A study of kinetics of moisture ingress to and release from active elements of capacitors would allow a better understanding of degradation mechanisms and is important for preventing failures. In this work, a technique for investigation of moisture sorption and desorption in solid chip tantalum capacitors that employs tantalum slugs as a humidity sensor have been developed and kinetics of the process analyzed for different types of capacitors at temperatures from room to 125 C. A model that relates diffusion characteristics of polymer cases and size of the slugs to characteristic times of moisture sorption has been developed. A strong effect of moisture on long-term degradation of reverse bias currents in MnO2 cathode capacitors has been demonstrated and physical mechanisms discussed.

Teverovsky, Alexander↗
NASA NTRS2001

InP MMIC chip set for power sources covering 86-170 GHz

We will present a Monolithic Millimeter-wave Integrated Circuit (MMIC) chip set which provides high output-power sources for driving diode frequency multipliers into the terahertz range. The chip set was fabricated at HRL Laboratories using a 0.l-μm gatelength InAI/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with an fmax above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range. In this paper, these high frequency HEMTs form the basis for power sources up to 170 GHz.

Ngo, Catherine↗
NASA NTRS1996

256X256 CMOS Active Pixel Sensor Camera-on-a-Chip

A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.

active↗
NASA NTRS1996

Progress in Voltage and Current Mode On-Chip Analog-to-Digital converters for CMOS Image Sensors

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 ??itch in a 1.2 ??-well CMOS process and a 40 ??itch in a 2 ??-well CMOS process. The successive approximation designs consume as little as 49 ??t a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental sigma-delta ADC test chips designed to be multiplied among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 ??t a 5 KHz.

analog-to-digital↗
NASA NTRS2018

LiveCheckHSI: a Hardware/Software Co-verification Tool for Hyperspectral Imaging Systems with Embedded System-on-Chip Instrument Avionics

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind state-of-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This paper describes hardware/software co-verification tools for the Xilinx Zynq-based control and data handling system that have been developed at the Jet Propulsion Laboratory (JPL) for visible-infrared imaging spectrometers. The system acquires and compresses images in real-time, in addition to programming the spectrometer (frame rate, exposure time), focus step motor, and heaters and reporting telemetry.

Dolman, David↗
NASA NTRS2018

High Performance Space Computing with System-on-Chip Instrument Avionics for Space-based Next Generation Imaging Spectrometers (NGIS).

The emergent technology of system-on-chip (SoC) devices promises lighter, smaller, cheaper, and more capable and reliable space electronic systems that could help to unveil some of the most treasured secrets in our universe. This technology is an improvement over the technology that is currently used in space applications, which lags behind stateof-the-art commercial-off-the-shelf (COTS) equipment by several generations. SoC technology integrates all computational power required by next-generation space exploration science instruments onto a single chip. This presentation will describe a Xilinx Zynq-based data acquisition, cloud-screening and compression computing system that has been developed at the Jet Propulsion Laboratory (JPL) for JPL’s Next Generation Imaging Spectrometers (NGIS). The Xilinx Zynq-based Alpha Data hardware assembly fits into a 120mm by 190m by 40mm assembly and uses 9 watts at peak performance. The computing element is a Xilinx Zynq Z7045Q which includes a Kintex-7 FPGA (equivalent to 3 RAD Virtex5 FPGAs in terms of logic cell resources) and dual-core ARM Cortex-A9 Processors (equivalent to 10 RAD750 Power PCs in term of processing capability).

Smith, Adam↗