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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Spacecraft optical disk recorder memory buffer control

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Hodson, Robert F.↗
NASA NTRS2003

Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

infrared↗
DOE OSTI2019

Hammerhead, an ultrahigh resolution ePix camera for wavelength-dispersive spectrometers

Wavelength-dispersive spectrometers (WDS) are often used in synchrotron and FEL applications where high energy resolution (in the order of eV) is important. Increasing WDS energy resolution requires increasing spatial resolution of the detectors in the dispersion direction. The common approaches are not ideal: using strip detectors loses the 2D position sensitivity (important for, e.g., background estimation) and the high counting rate; using pixel detectors with a small pitch results in complex charge sharing behaviour and typically have a small size. Developing pixel detectors with high aspect ratio and a small pitch in the wavelength dispersive direction would be ideal, however, it would require a substantial ASIC development. We present a new approach, with a novel sensor design using rectangular pixels with a high aspect ratio (between strips and pixels, further called “strixels”), and strixel redistribution to match the square pixel arrays of typical ASICs. This results in a sensor area of 17.4 mm × 77 mm, with a fine pitch of 25 µm in the horizontal direction resulting in 3072 columns and 176 rows. The sensors use ePix100 readout ASICs, leveraging their low noise (43 e - , or 180 eV rms). We present results obtained with a Hammerhead ePix100 camera, showing that the small pitch (25 µm) in the dispersion direction maximizes performance for both high and low photon occupancies, resulting in optimal WDS energy resolution. The low noise level at high photon occupancy allows precise photon counting, while at low occupancy, both the energy and the subpixel position can be reconstructed for every photon, allowing an ultrahigh resolution (in the order of 1 µm) in the dispersion direction and rejection of scattered beam and harmonics. Using strixel sensors with redistribution and flip-chip bonding to standard ePix readout ASICs results in ultrahigh position resolution (~1 µm) and low noise in WDS applications, leveraging the advantages of hybrid pixel detectors (high production yield, good availability, relatively inexpensive) while minimizing development complexity through sharing the ASIC, hardware, software and DAQ development with other versions of ePix cameras.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

FASDA: An FPGA-Aided, Scalable and Distributed Accelerator for Range-Limited Molecular Dynamics

Conducting long-term simulations of small molecules using Molecular Dynamics (MD) is crucial in drug design. However, traditional methods to accelerate the process including ASICs or GPUs, have limitations. ASICs are difficult to access, while publicly accessible GPU packages for MD have issues with more GPUs when processing small molecules, causing decreased performance. Conversely, FPGAs are renowned for their scalability and have been commonly used as accelerators for various applications, making them suitable for the task. Moreover, with the availability of FPGAs in the cloud, pharmaceutical developers can now access FPGA devices. The only missing piece is a design deployed for MD acceleration. Therefore, we present FASDA, the first FPGA-based MD accelerator available for community development. FASDA is designed to evaluate range-limited MD, which is the most resource-intensive and computationally demanding component in MD. It outperforms the state of-the-art GPU solution by 4.67x, significantly reducing the time for MD in drug design.

Wu, Chunshu↗
NASA NTRS1992

A DRAM compiler algorithm for high performance VLSI embedded memories

In many applications, the limited density of the embedded SRAM does not allow integrating the memory on the same chip with other logic and functional blocks. In such cases, the embedded DRAM provides the optimum combination of very high density, low power, and high performance. For ASIC's to take full advantage of this design strategy, an efficient and highly reliable DRAM compiler must be used. The embedded DRAM architecture, cell, and peripheral circuit design considerations and the algorithm of a high performance memory compiler are presented .

Eldin, A. G.↗
NASA NTRS2002

Software Safety Assurance of Programmable Logic

Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

Berens, Kalynnda↗
NASA NTRS2018

Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.

Design for reliability (DFR)↗
NASA NTRS1991

An application specific integrated circuit based multi-anode microchannel array readout system

Size reduction of two new multi-anode microchannel array (MAMA) readout systems is described. The systems are based on two analog and one digital application specific integrated circuits (ASICs). The new readout systems reduce volume over previous discrete designs by 80 percent while improving electrical performance on virtually every significant parameter. Emphasis is made on the packaging used to achieve the volume reduction. Surface mount technology (SMT) is combined with modular construction for the analog portion of the readout. SMT reliability concerns and the board area impact of MIL SPEC SMT components is addressed. Package selection for the analog ASIC is discussed. Future sytems will require even denser packaging and the volume reduction progression is shown.

Smeins, Larry G.↗
DOE OSTI2025

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗
NASA NTRSDate not supplied

Coherent Architectures for Free-Space Optical Communications

Custom coherent architectures can provide many advantages for FSO communications systems through co-development of integrated photonics, ASIC-or FPGA-based DSP algorithms, and system design to mitigate atmospheric turbulence and reduce pointing requirements.

David J Geisler↗
DOE OSTI2025

Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators using HLS4ML

With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.

Di Guglielmo, Giuseppe [Fermilab]↗
NASA NTRSDate not supplied

Design and Performance of the CdZnTe VFG Imaging Calorimeter Prototype for Gamma-ray Astronomy

We present the design and first results of the CdZnTe Imaging calorimeter prototype. The CdZnTe Imaging calorimeter has been designed for use in large astrophysical gamma-ray space instruments, and we report here on a small prototype built to validate the approach. The calorimeter is based on virtual Frisch-grid drift-bar CdZnTe detectors. The design is modular, such that multiple crates of 16 bars, each served by a single ASIC, can be arranged in to different configurations depending on the specific requirements for an instrument. The modules are plugged into the readout motherboard in the designed configuration for a given instrument. The detectors are capable of measuring the interaction point of an incident photon in three dimensions and the energy deposited. In this work, we have designed and built a prototype consisting of 4 by 4 module array and have tested it with various radioactive sources to measure its position and energy resolution. The preliminary results demonstrate ~1% FWHM energy resolution and 1-2 mm position resolution for 662 keV photons (Cs137), subject to the further improvement by applying various corrections. We tested the module with a “conventional” analog ASIC readout as well as a wave-front sampling ASIC to compare the results, which is critical for the optimization of the future instrument.

A. A. Moiseev↗
DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗
NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗
DOE OSTI2019

Development of a large active area beam telescope based on the SiD microstrip sensor

A beam telescope as one of the most important and often requested test beam equipment provides particle tracking to test beam users. At the DESY II test beam facility, a new beam telescope called Lycorisbased on a microstrip sensor has been designed to address the user demands for momentum measurement in a 1 T solenoid magnet or large area tracking with limited space (3.5 cm between the potential user device and the magnet inner wall). Lycorisis designed to provide a high-precision resolution of at least ~10 µm along the bending direction, and a large active area of 10x10 cm 2 to cover at least 90% of the beam particles at energies of 1-6 GeV. The microstrip sensor was originally designed for the Silicon Detector (SiD) at the International Linear Collider (ILC), which adopted a hybrid-less design, i.e. a second metallization layer is used to route signals from strips to the bump-bonded ASIC, and from the ASIC to a wire-bond pad to the outside. This hybrid-less arrangement eliminates the need for a complex hybrid design, and its functioning is first-time tested in this project. The performance of the sensor modules was firstly tested in the lab then at the DESY II test beam facility in August/September 2018, and the results will be presented here. In addition, a summary will be given at the end with an overview of the ongoing test beam campaign of the Lycorisprototype in February 2019.

47 OTHER INSTRUMENTATION↗
NASA NTRS2004

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

flight computers↗
NASA NTRS2015

Data Concentrator

Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.

Willett, Mike↗