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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Design of Monolithic Bi-Layer High-Z PAL-Si Hard X-ray CMOS Image Sensors for Quantum Efficiency Enhancement

This article experimentally investigates the inception of an innovative hard X-ray photon energy attenuation layer (PAL) to advance high-energy X-ray detection (20–50 keV). A bi-layer design with a thin film high-Z PAL on the top and Si image sensor on the bottom has previously demon-strated quantum yield enhancement via computational methods by the principle of photon energy down conversion (PEDC), where high-energy X-ray photon energies are attenuated via inelastic scattering down to ≤10 keV, which is suitable for efficient photoelectric absorption by Si. Quantum yield enhancement has been experimentally confirmed via a preliminary demonstration using PAL-integrated Si-based CMOS image sensors (Si CIS). Furthermore, substituting the high-Z PAL with a lower-Z material—Sn—and alternatively coupling it with a conventional scintillator ma-terial—Lutetium-yttrium oxyorthosilicate (LYSO)—have been compared to demonstrate the most prominent efficacy of monolithic integration of high-Z PAL on Si CIS to detect hard X-rays, paving the way for next-generation high-energy X-ray detection methods.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

CMOS-Compatible Ultrathin Superconducting NbN Thin Films Deposited by Reactive Ion Sputtering on 300 mm Si Wafer

We report a milestone in achieving large-scale, ultrathin (~5 nm) superconducting NbN thin films on 300 mm Si wafers using a high-volume manufacturing (HVM) industrial physical vapor deposition (PVD) system. The NbN thin films possess remarkable structural uniformity and consistently high superconducting quality across the entire 300 mm Si wafer, by incorporating an AlN buffer layer. High-resolution X-ray diffraction and transmission electron microscopy analyses unveiled enhanced crystallinity of (111)-oriented δ-phase NbN with the AlN buffer layer. Notably, NbN films deposited on AlN-buffered Si substrates exhibited a significantly elevated superconducting critical temperature (~2 K higher for the 10 nm NbN) and a higher upper critical magnetic field or H c2 (34.06 T boost in H c2 for the 50 nm NbN) in comparison with those without AlN. These findings present a promising pathway for the integration of quantum-grade superconducting NbN films with the existing 300 mm CMOS Si platform for quantum information applications.

36 MATERIALS SCIENCE↗
NASA NTRS1976

CMOS-compatible tristate cable driver

Device provides noise immunity, draws zero standby power, and improves performance where same bus connects several pieces of CMOS equipment.

Pryor, R. L.↗
NASA NTRS1976

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Cliff, R. A.↗
NASA NTRS1976

Successful large-scale use of CMOS devices on spacecraft traveling through intense radiation belts

This paper describes the environmental models of the radiation belts and computational techniques which have been developed for predicting the radiation hazards for spacecraft. These data and techniques are then applied to the Atmosphere Explorer 51 spacecraft to explain its successful survival for more than 18 months in a severe environment. In particular, the results of the analysis are used to explain the performance of some 2400 CMOS devices, and consequently, they demonstrate the reliability of this device technology in spacecraft systems.

Brucker, G. J.↗
NASA NTRS1976

Diurnal measurements with prototype CMOS Omega receivers

Diurnal signals from eight omega channels have been monitored at 10.2 KHz for selected station pairs. All eight Omega stations have been received at least 50 percent of the time over a 24 hour period during the month of October 1976. The data presented confirm the expected performance of the CMOS omega sensor processor in being able to digsignals out of a noisy environment. Of particular interest are possibilities for use of antipodal reception phenomena and a need for some ways of correcting for multi-modal propagation effects.

Burhans, R. W.↗
NASA NTRS1976

Accelerated life testing effects on CMOS microcircuit characteristics, phase 1

An accelerated life test of sufficient duration to generate a minimum of 50% cumulative failures in lots of CMOS devices was conducted to provide a basis for determining the consistency of activation energy at 250 C. An investigation was made to determine whether any thresholds were exceeded during the high temperature testing, which could trigger failure mechanisms unique to that temperature. The usefulness of the 250 C temperature test as a predictor of long term reliability was evaluated.

Maximow, B.↗
NASA NTRS1978

Curve tracer checks CMOS IC's

Conventional transistor curve tracer can speed up failure analysis of CMOS integrated circuits by displaying transfer characteristics while device is subjected to vibration or environmental testing. Failures that show up as change in threshold voltage or transfer characteristics are quickly detected.

Kizer, F.↗
NASA NTRS1979

CMOS-array design-automation techniques

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Feller, A.↗
NASA NTRS1977

Prediction and measurement results of radiation damage to CMOS devices on board spacecraft

Final results from the CMOS Radiation Effects Measurement (CREM) experiment flown on Explorer 55 are presented and discussed, based on about 15 months of observations and measurements. Conclusions are given relating to long-range annealing, effects of operating temperature on semiconductor performance in space, biased and unbiased P-MOS device degradation, unbiased n-channel device performance, changes in device transconductance, and the difference in ionization efficiency between Co-60 gamma rays and 1-Mev Van de Graaff electrons. The performance of devices in a heavily shielded electronic subsystem box within the spacecraft is evaluated and compared. Environment models and computational methods and their impact on device-degradation estimates are being reviewed to determine whether they permit cost-effective design of spacecraft.

Stassinopoulos, E. G.↗
NASA NTRS1979

CMOS circuit-fabrication handbook

Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.

Bouldin, D. L.↗
NASA NTRS1979

Development of CMOS integrated circuits

Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

Bertino, F.↗
NASA NTRS1980

CMOS analog switches for adaptive filters

Adaptive active low-pass filters incorporate CMOS (Complimentary Metal-Oxide Semiconductor) analog switches (such as 4066 switch) that reduce variation in switch resistance when filter is switched to any selected transfer function.

Dixon, C. E.↗
NASA NTRS1979

Electrical Characterization of Hughes HCMP 1852D and RCA CDP1852D 8-bit, CMOS, I/O Ports

Twenty-five Hughes HCMP 1852D and 25 RCA CDP1852D 8-bit, CMOS, I/O port microcircuits underwent electrical characterization tests. All electrical measurements were performed on a Tektronix S-3260 Test System. Before electrical testing, the devices were subjected to a 168-hour burn-in at 125 C with the inputs biased at 10V. Four of the Hughes parts became inoperable during testing. They exhibited functional failures and out-of-range parametric measurements after a few runs of the test program.

Stokes, R. L.↗
NASA NTRS1980

Accelerated life testing effects on CMOS microcircuit characteristics

This report covers the time period from May 1976 to December 1979 and encompasses the three phases of accelerated testing: Phase 1, the 250 C testing; Phase 2, the 200 C testing; and Phase 3, the 125 C testing. The duration of the test in Phase 1 and Phase 2 was sufficient to take the devices into the wear out region. The wear out distributions were used to estimate the activation energy between the 250 C and the 200 C test temperatures. The duration of the 125 C test, 20,000 hours, was not sufficient to bring the test devices into the wear out region; consequently the third data point at 125 C for determining the consistency of activation energy could not be obtained. It was estimated that, for the most complex of the three device types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment was assessed. Guidelines for the development of accelerated life test conditions were proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life test characteristics of CMOS microcircuits was explored in Phase 4 of this study and is attached as an appendix to this report.

Source record↗
NASA NTRS1980

Accelerated life testing effects on CMOS microcircuit characteristics

The 250 C, 200C and 125C accelerated tests are described. The wear-out distributions from the 250 and 200 C tests were used to estimate the activation energy between the two test temperatures. The duration of the 125 C test was not sufficient to bring the test devices into the wear-out region. It was estimated that, for the most complex of the three devices types, the activation energy between 200 C and 125 C should be at least as high as that between 250 C and 200 C. The practicality of the use of high temperature for the accelerated life tests from the point of view of durability of equipment is assessed. Guidlines for the development of accelerated life-test conditions are proposed. The use of the silicon nitride overcoat to improve the high temperature accelerated life-test characteristics of CMOS microcircuits is described.

Source record↗
NASA NTRS1981

Assessment of high temperature metallizations for I(2)L and CMOS technologies

High temperature barrier metallizations were assessed and tested for I(2)L and CMOS applications. Life tests were accelerated to 375 C in view of the -55 C to +300 C temperature range established for engine-located electronics without fuel cooling. The gold-refractory metallizations evaluated were Au-TiW-PtSi, Au-TiW/TiO2/TiW-PtSi and Au-TiW(N)-PtSi. These metallization systems were thermally annealed to at least 375 C for up to 250 hours. The critical requirement for stable diffusion barrier is the TiW grain size. Small grain (250A-500A) films were observed to be stable up to 375 C. Deposition to TiW diffusion barrier in the presence of oxygen and nitrogen also results in an effective diffusion barrier. Auger electron spectroscopy profiles of the PtSi indicates some penetration by the TiW. In the case of PtSi/TiW interface, the redistribution of oxygen further passivates the system by forming a TiO2 layer at the interface.

Christou, A.↗
NASA NTRS1982

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Kolasinski, W. A.↗