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At least 1,423 records · Page 79

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NASA NTRS1979

Linear Approximation SAR Azimuth Processing Study

A segmented linear approximation of the quadratic phase function that is used to focus the synthetic antenna of a SAR was studied. Ideal focusing, using a quadratic varying phase focusing function during the time radar target histories are gathered, requires a large number of complex multiplications. These can be largely eliminated by using linear approximation techniques. The result is a reduced processor size and chip count relative to ideally focussed processing and a correspondingly increased feasibility for spaceworthy implementation. A preliminary design and sizing for a spaceworthy linear approximation SAR azimuth processor meeting requirements similar to those of the SEASAT-A SAR was developed. The study resulted in a design with approximately 1500 IC's, 1.2 cubic feet of volume, and 350 watts of power for a single look, 4000 range cell azimuth processor with 25 meters resolution.

Lindquist, R. B.↗

NASA NTRS1979

Software design and documentation language, revision 1

The Software Design and Documentation Language (SDDL) developed to provide an effective communications medium to support the design and documentation of complex software applications is described. Features of the system include: (1) a processor which can convert design specifications into an intelligible, informative machine-reproducible document; (2) a design and documentation language with forms and syntax that are simple, unrestrictive, and communicative; and (3) methodology for effective use of the language and processor. The SDDL processor is written in the SIMSCRIPT II programming language and is implemented on the UNIVAC 1108, the IBM 360/370, and Control Data machines.

Kleine, H.↗

NASA NTRS1977

Coherent optical processing of synthetic aperture radar data

Consideration is given to the data processing algorithm used in synthetic aperture radar (SAR) systems. Examples are presented of radar imagery obtained with the ERIM X-band SAR system and processed with a precision optical processor. An optical recording of the data is the input to the coherent optical processing channel. The encoding technique, spatial format, and quality of the stored data are discussed. Several optical processor configurations are outlined, noting particularly the tilted-plane system. A scanning photodetector serves to convert the optical processor output image data into an electronic signal stream. Solid-state two-dimensional photodetector arrays may provide this function at increased speeds and with greater accuracy.

Cindrich, I.↗

NASA NTRS1979

Laser Doppler anemometer diagnostics in unsteady flows

The application of the laser Doppler anemometer (LDA) to unsteady flows is discussed with respect to necessary features of the signal processor, properties of the optical system, and the character of the flow under investigation. The discussion of signal processors includes consideration of frequency trackers, counter-type processors, particle properties, data rates, and statistics. Secondly, diffraction limitations for an optical system are viewed with respect to spatial resolution. Finally, the total velocity field is decomposed into its subfields and the feasibility of, criteria for, and possible types of conditional sampling are defined. Several reported LDA experiments using conditional sampling are presented to demonstrate the different techniques that may be used.

Orloff, K. L.↗

NASA NTRS1980

Software design and documentation language

Language supports design and documentation of complex software. Included are: design and documentation language for expressing design concepts; processor that produces intelligble documentation based on design specifications; and methodology for using language and processor to create well-structured top-down programs and documentation. Processor is written in SIMSCRIPT 11.5 programming language for use on UNIVAC, IBM, and CDC machines.

Kleine, H.↗

NASA NTRS1979

Shuttle orbiter S-band payload communications equipment design evaluation

The analysis of the design, and the performance assessment of the Orbiter S-band communication equipment are reported. The equipment considered include: network transponder, network signal processor, FM transmitter, FM signal processor, payload interrogator, and payload signal processor.

Springett, J. C.↗

NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗

NASA NTRS1980

An experimental distributed microprocessor implementation with a shared memory communications and control medium

The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.

Mejzak, R. S.↗

NASA NTRS1980

Considerations on real-time processing of spaceborne synthetic aperture radar data

This paper comprises a description of Synthetic Aperture Radar (SAR) processing approaches and a discussion on the processor complexity measures. The objective of the paper is to provide basic system knowledge on the design of a real-time signal processor for spaceborne synthetic aperture radar. A review of SAR sensor performance capability and general electronic processing approaches will be given first. The discussion of SAR processor complexity is divided into two areas: the arithmetic complexity and the control complexity. A generalized treatment of these subjects is provided. The results could be readily extended to special cases.

Wu, C.↗

NASA NTRS1980

Parallel processing implementations of a contextual classifier for multispectral remote sensing data

The applicability of parallel processing schemes to the implementation of a contextual classification algorithm which exploits the spatial and spectral context of a multispectral remote sensing pixel to achieve classification is examined. Two algorithms for classifying each multivariate pixel taking into account the probable classifications of neighboring pixels are presented which make use of a size three horizontally linear neighborhood, and the serial computational complexity of the more efficient algorithm is shown to grow in proportion to the number of pixels and the cube of the number of possible categories. The implementation of the more efficient algorithm on a CDC Flexible Processor system and on a multimicroprocessor system such as the proposed PASM is then discussed. It is noted that the use of N processors to perform the calculations N times faster than a single processor overcomes the principal disadvantage of contexual classifiers, i.e., their computational complexity.

Siegel, H. J.↗

NASA NTRS1982

The SPAR thermal analyzer: Present and future

The SPAR thermal analyzer, a system of finite-element processors for performing steady-state and transient thermal analyses, is described. The processors communicate with each other through the SPAR random access data base. As each processor is executed, all pertinent source data is extracted from the data base and results are stored in the data base. Steady state temperature distributions are determined by a direct solution method for linear problems and a modified Newton-Raphson method for nonlinear problems. An explicit and several implicit methods are available for the solution of transient heat transfer problems. Finite element plotting capability is available for model checkout and verification.

Marlowe, M. B.↗

NASA NTRS1982

The P-POD Project

The programmable pilot oriented display (P-POD), a multiprocessor based flight information processing and display unit, is discussed. Communication protocols between the three Z-80 processors inside P-POD are reviewed. The interface between the video processor, P2, and the main processor, P1, was tested. Hardware and software were revised. Data flow between P1 and P2 is illustrated. While running diagnostic routines to exercise the P1/P2 interface at maximum speed an intermittent failure was observed. A check of possible noise sources or race conditions in the hardware did not reveal the source of this failure. Possible software timing problems were also fully investigated. To eliminate the effects of this type of failure a performance monitor routine was used to detect these occasional failures and correct them. The data transmission cycle between P1/P2 is either allowed to continue normal operation or is re-initialized and restarted when an error is detected.

Littlefield, J. A.↗

NASA NTRS1982

Electrically reconfigurable logic array

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Agarwal, R. K.↗

NASA NTRS1983

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Strohkorb, G. A.↗

NASA NTRS1983

Data highway terminal controller

A data highway terminal controller with transmission controllers assigned to each processor in a set of multiple processors is described. Shared-use terminals are loop connected to the processors via the controllers.

Yoshimoto, T.↗

NASA NTRS1982

Geology and image processing

Digital image processing for geological applications will be integrated with geographic information systems and data base management systems. While multiband data sets from radar and multispectral scanners will make extreme demands on memory, bus and processor architectures, it is expected that array processors and VLSI/VHSIC dedicated function chips will allow the use of fast Fourier transform and classification algorithms. It is anticipted that, as processor power increases, the weakest link of a processing system will become the analyst who uses it. Human engineering of systems is therefore recommended for the most effective utilization of remotely sensed geologic data.

Daily, M.↗

NASA NTRS1983

Simplified power processing for ion-thruster subsystems

A review of the thruster/power-processor-interface requirements for (mercury and inert gas) ion-thrusters, an evaluation of various approaches to simplifying the power-processor circuitry, and the test results of the recently developed 8-cm mercury-ion-thruster simplified power-processor unit (SPPU) are presented. The SPPU demonstrates the feasibility of stable thruster operation using highly simplified power-processing techniques and achieves an approximately tenfold reduction in the electronic parts count when compared to the existing power-processor unit (PPU) used in the Hughes/NASA Lewis Research Center 8-cm-diameter (mercury) Ion Auxiliary Propulsion Subsystem (IAPS).

Wessel, F. J.↗

NASA NTRS1982

Onboard processing for a 30/20 GHz communications satellite

A systems configuration for the baseband processor for a TDMA communications satellite utilizing the 30 GHz uplink and 20 GHz downlink bands will be discussed. The baseband processor functions include QPSK burst demodulation, convolutional decoding, data routing, encoding, QPSK modulation, and antenna steering. The performance of the burst demodulator will be examined. Power and weight estimates for the baseband processor will be presented.

Reisenfeld, S.↗