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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Fault clearing currents were achieved and maintained at discharge rates from C/2 to C/3 at high and low states of charge. The fault clearing plateau voltage is strong function of: discharge current, and voltage-prior-to-the-fault-clearing-event and a weak function of state of charge. Voltage performance, for the range of conditions reported, is summarized.
The test results of measurements performed on two different sizes of ferroelectric random access memory (FeRAM) suggest the degradation is due to the low radiation tolerance of sense amplifiers and reference voltage generators which are based on commercial complementary metal oxide semiconductor (CMOS) technology. This paper presents total ionizing dose (TID) testing of 64Kb Ramtron FM1608 and 256Kb Ramtron FM1808.
Integrated arrays of microscopic solid-state batteries have been demonstrated in a continuing effort to develop microscopic sources of power and of voltage reference circuits to be incorporated into low-power integrated circuits. Perhaps even more importantly, arrays of microscopic batteries can be fabricated and tested in combinatorial experiments directed toward optimization and discovery of battery materials. The value of the combinatorial approach to optimization and discovery has been proven in the optoelectronic, pharmaceutical, and bioengineering industries. Depending on the specific application, the combinatorial approach can involve the investigation of hundreds or even thousands of different combinations; hence, it is time-consuming and expensive to attempt to implement the combinatorial approach by building and testing full-size, discrete cells and batteries. The conception of microbattery arrays makes it practical to bring the advantages of the combinatorial approach to the development of batteries.
An improved technique, and electronic circuitry to implement the technique, have been developed for a military-standard electromagnetic-compatibility (EMC) test in which one analyzes susceptibility to low-frequency ripple conducted into the equipment under test via a DC power line. In the traditional technique for performing the particular test, the ripple is coupled onto the DC power line via a transformer. Depending upon some design details of the equipment under test, the inductance of the transformer can contribute a degree of instability that results in an oscillation of amplitude large enough to destroy the equipment. It is usually possible to suppress the oscillation by connecting a damping resistor to the primary terminals of the ripple-injection transformer. However, it is important to emphasize the usually in the preceding sentence: sometimes, the resistive damping becomes insufficient to suppress destructive oscillation. In addition, undesirably, the resistor contributes to power dissipation and power demand, and thereby also necessitates the use of a larger ripple voltage amplifier. Yet another disadvantage of the transformer-coupling technique is that the transformer introduces low-frequency distortion of the injected ripple voltage. The improved technique makes it possible to inject ripple with very low distortion at low frequency, without inducing oscillation. In this technique, a transformer is not used: Instead, power is fed to the equipment under test via series power field-effect transistors (FETs) controlled by a summing operational amplifier. One of the inputs to the amplifier controls the DC component of the power-line voltage; the other input, generated by an external oscillator, controls the ripple component. The circuitry for implementing this technique includes panel displays, an internal power supply for the operational amplifier and panel displays, and amplitude controls for the DC and ripple powerline voltage components.
Most contemporary device models predict that an acceptor concentration of at least 10^16 cm^-3 is required to reach an open circuit voltage of 1 V in polycrystalline CdTe-based solar cells. While copper has traditionally been used as the de facto p-type dopant in polycrystalline cadmium telluride (CdTe) and cadmium selenide telluride (CdSeTe), reaching high acceptor concentrations has proved to be challenging in such devices due to significant dopant compensation. The acceptor concentration in copper-doped CdTe and CdSeTe typically ranges from 10^13 to 10^15 cm^-3 and routinely exhibit low external radiative efficiencies below 0.01%, limiting their implied voltage (i.e., quasi-Fermi level splitting) to approximately 900 mV. As an alternative to copper, this work explores the use of arsenic as a p-type dopant for CdTe and CdSeTe. Using a novel technique in which a thin layer of arsenic-containing material is deposited and used as a reservoir for arsenic to diffuse into a front layer of previously undoped material, this contribution demonstrates that high external radiative efficiencies are achievable, a direct result of combined high acceptor concentrations and long minority-carrier lifetimes in the absorber. This leads to improved implied voltages, and indicates that As-doping represents a promising pathway towards improving the external voltage of CdSeTe/CdTe solar cells.
Single, variable, transformer/choke device does work of several. Technique reduces drawer assembly physical size and design and manufacturing cost. Device provides power, voltage current and impedance regulation while maintaining maximum control of linearity and ensuring extremely low ripple. Nulling is controlled to very fine degree.
This paper presents the analysis and implementation of a predictive control method for dc-link regulation and voltage balance in a cascaded modular reduced dc-link solid-state transformer (SST). Passive components like bulky dc links limit the power density of power converters, especially medium-voltage (MV) SST. Reduced dc-link or low-inertia converters can dramatically reduce the size, cost, and weight by tolerating larger dc-link ripples and improve the reliability with electrolytic capacitor-less dc link. However, a small dc link leads to tight coupling between the input and the output stages, which is a challenge for control design. In stacked low-inertia converters (SLIC), the low-inertia converter modules are stacked for MV applications, resulting in coupling between the modules and making the control more challenging. A new model predictive control method which can achieve deadbeat regulation on the dc link without weighting factors has been proposed to address this novel problem. This paper focuses on analyzing the condition of the low-inertia dc link up to 80% ripple, the robustness of the control under parameter mismatches, high-order terms, and important implementation issues such as model-based sampling and computation delay compensation. Significantly, the high-order terms are introduced because of the large dc-link ripple. These high-order terms are unique to the SLIC and negligible in conventional high-inertia converters. A discrete-time large-signal model is built to capture the dc-link’s nonlinear dynamics, and the eigenvalues of a small-signal Jacobian matrix are analyzed with Floquet theory to evaluate stability, using the modular soft-switching solid-state transformer (M-S4T) as an example of the SLIC. Simulation and experimental results of an MVDC M-S4T verify the analysis and the predictive control method. Finally, the general application of the predictive control to low-inertia converters is compared against a conventional PI controller using a reduced dc-link active-front-end (AFE) rectifier as an example.
Specific contact resistivities for as-fabricated Au contacts on n-p InP solar cells are typically in the 10(exp -3) ohm/sq cm range, but contact resistivities in the 10(exp -6) ohm/sq cm range can be obtained if the cells are heat treated at 400 C for a few minutes. This heat treatment, however, results in a dramatic drop in the open circuit voltage of the cell due to excessive dissolution of the emitter into the metallization. It was found that low values of contact resistivity can be secured without the accompanying drop in the open circuit voltage by adding Ga and In in the Au metallization. It is shown that Au contacts containing as little as 1 percent atomic Ga can suppress the reaction that takes place at the metal-InP interface during heat treatment, while exhibiting contact resistivity values in the low 10(exp -5) ohm/sq cm. Detailed explanations for the observed superior thermal stability of these contacts are presented.
Commercial-Off-The-Shelf (COTS) multilayer ceramic chip capacitors (MLCCs) are continually evolving to reduce physical size and increase volumetric efficiency. Designers of high reliability aerospace and military systems are attracted to these attributes of COTS MLCCs and would like to take advantage of them while maintaining the high standards for long-term reliable operation they are accustomed io when selecting military qualified established reliability (MIL-ER) MLCCs. However, MIL-ER MLCCs are not available in the full range of small chip sizes with high capacitance as found in today's COTS MLCCs. The objectives for this evaluation were to assess the long-term performance of small case size COTS MLCCs and to identify effective, lower-cost product assurance methodologies. Fifteen (15) lots of COTS X7R dielectric MLCCs from four (4) different manufacturers and two (2) MIL-ER BX dielectric MLCCs from two (2) of the same manufacturers were evaluated. Both 0805 and 0402 chip sizes were included. Several voltage ratings were tested ranging from a high of 50 volts to a low of 6.3 volts. The evaluation consisted of a comprehensive screening and qualification test program based upon MIL-PRF-55681 (i.e., voltage conditioning, thermal shock, moisture resistance, 2000-hour life test, etc.). In addition, several lot characterization tests were performed including Destructive Physical Analysis (DPA), Highly Accelerated Life Test (HALT) and Dielectric Voltage Breakdown Strength. The data analysis included a comparison of the 2000-hour life test results (used as a metric for long-term performance) relative to the screening and characterization test results. Results of this analysis indicate that the long-term life performance of COTS MLCCs is variable -- some lots perform well, some lots perform poorly. DPA and HALT were found to be promising lot characterization tests to identify substandard COTS MLCC lots prior to conducting more expensive screening and qualification tests. The results indicate that lot- specific screening and qualification are still recommended for high reliability applications. One significant and concerning observation is that MIL- type voltage conditioning (100 hours at twice rated voltage, 125 C) was not an effective screen in removing infant mortality parts for the particular lots of COTS MLCCs evaluated.
A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.
Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to protect these devices from overcurrent during low-inductance fault events. The use of an air core Rogowski coil topology was explored to see if it could mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-tophase fault, tested up to DC link voltages of 1 kV.
Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have emerged as promising non-volatile memory elements for microelectronics, compatible with back end of line (BEOL) complementary–metal–oxide semiconductor fabrication. This study investigates asymmetric electrode TaN/HZO/Ta devices with a 6 nm thick HZO layer as FTJs for multistate resistive memory applications. The individual FTJs exhibit a resistance ratio exceeding 10× when utilized as a binary state device, with pulsing between −1.7 and +1.4 V to set the high resistance state (HRS) and low resistance state (LRS), respectively. Following with reduced write voltage pulses allows the ferroelectric device to operate with a selection of over 32 distinct resistance states (2 5 bits) between the LRS and HRS. This work then explores the stability of the resistance states during write/read pulse cycling, along with the stability of the state after multiple read pulses. Accessing the multibit state shows stability within 50 reads with the binary state remaining stable for more than 4000 reads pulses. With their multistate tunability and versatility, FTJs hold promise as BEOL memory elements for compute-in-memory (CiM) arrays, binary digital memory, or weighted vector matrix multiplication applications with low power consumption during computations.
Poly (ethylene oxide) (PEO)-based solid-state polymer electrolytes (SPEs) show prospects in all-solid-state lithium metal batteries. However, they suffer from low ionic conductivity at room temperature and interfacial instability with high voltage cathodes for long-term cycling. In this work, top-down fluorinated PEOs (F-PEOs) for the all-solid-state electrolytes, which are scalable and cost-effective, are developed to improve the battery performance. We demonstrate, that by enhancing the disordering of the F-PEO matrix, the SPE achieves a maximum Li + conductivity of 1.1 x 10 -4 S cm -1 at 40 °C, which is 20 times higher than the baseline. By forming robust cathode/SPE and Li/SPE interfaces, the F-PEO-based SPEs demonstrate stable cycling in the LiFePO 4 /Li and LiNi 0·8 Mn 0·1 Co 0·1 O 2 /Li (3-4.4 V, 500 cycles, capacity retention of 91.6%) based all-solid-state batteries at 40 °C. Therefore, our work highlights the significance of "disordering engineering" for energy storage materials.
The purpose of this testing was to characterize Analog Devices’ AD8065 FastFET amplifier for low-dose rate (LDR) total ionizing dose (TID) response based on the Lucy project requirements and will be used on the L’ORRI instrument being built by Johns Hopkins University Applied Physics Lab. The AD8065 is a voltage feedback amplifier with FET inputs developed with the proprietary eXtra Fast Complementary Bipolar (XFCB) process. The amplifier boasts low noise operation and very high input impedance with a wide supply voltage range.
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In this work, we demonstrate how perovskite hysteresis can result in permanent reductions in power output in perovskite/silicon tandem modules—including irreversible hotspot-induced damage—from only brief periods of shading. We show that reverse bias events in which a perovskite cell is biased above a threshold voltage—which in this work we find to be as low as –1.1 V—produces a temporary reduction in power output that is of sufficient magnitude to keep the cell pinned in reverse bias after the shading event ends. As a hysteretic phenomena, this crucial failure mode may be overlooked by static models of perovskite-based solar cells. Higher reverse bias voltages exacerbate the temporary reduction in short-circuit photocurrent, which is also sensitive to the level of illumination under reverse bias. Numerical device modelling demonstrates that this effect is consistent with our understanding of perovskite hysteresis as a consequence of mobile ion-electron coupling controlling rates of non-radiative recombination over time. Measurements of the dynamic response of single-junction perovskite cells are extrapolated to two-terminal and four-terminal perovskite/silicon tandem module modelling. We validate these models with measurements from an equivalent electronic circuit that represents a two-terminal perovskite–silicon tandem mini module. Two module-level solutions are discussed that address this issue, which includes increasing the number of bypass diodes and choosing better suited silicon bottom cells with higher shunter resistance in two-terminal tandem modules.
Circuit converts an rms, ac voltage to a proportional dc voltage with good accuracy over a voltage range of approximately 6-1. It incorporates a pair of vacuum thermocouples in a dc feedback circuit.
To simulate the behavior of a high voltage solar cell array in the ionospheric plasma environment, the large (90 ft x 55 ft diameter) vacuum chamber was used to measure the high-voltage plasma interactions of a 3 ft x 30 ft conductive panel. The chamber was filled with Nitrogen and Argon plasma at electron densities of up to 1,000,000 per cu cm. Measurements of current flow to the plasma were made in three configurations: (a) with one end of the panel grounded, (b) with the whole panel floating while a high bias was applied between the ends of the panel, and (c) with the whole panel at high negative voltage with respect to the chamber walls. The results indicate that a simple model with a constant panel conductivity and plasma resistance can adequately describe the voltage distribution along the panel and the plasma current flow. As expected, when a high potential difference is applied to the panel ends more than 95% of the panel floats negative with respect to the plasma.