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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,405 records · Page 78
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Silicon Materials Task of the Low Cost Solar Array Project, Phase 3. Effect of Impurities and Processing on Silicon Solar Cells

The effects of impurities, various thermochemical processes, and any impurity process interactions on the performance of terrestrial silicon solar cells are defined. Determinations of the segregation coefficients of tungsten, tantalum, and cobalt for the Czochralski pulling of silicon single crystals are reported. Sensitive neutron activation analysis was used to determine the metal impurity content of the silicon while atomic absorption was used to measure the metal content of the residual liquid from which the doped crystals were grown. Gettering of Ti doped silicon wafers improved cell performance by one to two percent for the highest temperatures and longest times. The HCl is more effective than POCl3 treatments for deactivating Ti but POCl3 and HCl produced essentially identical results for Mo or Fe.

Hopkins, R. H.↗
NASA NTRS1979

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Jones, G. T.↗
NASA NTRS1978

Array Automated Assembly Task Low Cost Silicon Solar Array Project, Phase 2

Progress in the development of solar cells and module process steps for low-cost solar arrays is reported. Specific topics covered include: (1) a system to automatically measure solar cell electrical performance parameters; (2) automation of wafer surface preparation, printing, and plating; (3) laser inspection of mechanical defects of solar cells; and (4) a silicon antireflection coating system. Two solar cell process steps, laser trimming and holing automation and spray-on dopant junction formation, are described.

Rhee, S. S.↗
NASA NTRS1979

Silicon-on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

The technical and economic feasibility of producing solar cell-quality silicon was investigated. This was done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress in the following areas was demonstrated: (1) fabricating a 10 sq cm cell having 9.9 percent conversion efficiency; (2) producing a 225 sq cm layer of sheet silicon; and (3) obtaining 100 microns thick coatings at pull speed of 0.15 cm/sec, although approximately 50 percent of the layer exhibited dendritic growth.

Chapman, P. W.↗
NASA NTRS1979

Design, processing and testing of LSI arrays: Hybrid microelectronics task

Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.

Himmel, R. P.↗
NASA NTRS1979

Investigation of Proposed Process Sequence for the Array Automated Assembly Task, Phase 2

The technological readiness of the proposed process sequence was reviewed. Process steps evaluated include: (1) plasma etching to establish a standard surface; (2) forming junctions by diffusion from an N-type polymeric spray-on source; (3) forming a p+ back contact by firing a screen printed aluminum paste; (4) forming screen printed front contacts after cleaning the back aluminum and removing the diffusion oxide; (5) cleaning the junction by a laser scribe operation; (6) forming an antireflection coating by baking a polymeric spray-on film; (7) ultrasonically tin padding the cells; and (8) assembling cell strings into solar circuits using ethylene vinyl acetate as an encapsulant and laminating medium.

Mardesich, N.↗
NASA NTRS1979

Process Feasibility Study in Support of Silicon Material Task 1

Analysis of process system properties was continued for silicon source materials under consideration for producing silicon. The following property data are reported for dichlorosilane which is involved in processing operations for silicon: critical constants, vapor pressure, heat of vaporization, heat capacity, density, surface tension, thermal conductivity, heat of formation and Gibb's free energy of formation. The properties are reported as a function of temperature to permit rapid engineering usage. The preliminary economic analysis of the process is described. Cost analysis results for the process (case A-two deposition reactors and six electrolysis cells) are presented based on a preliminary process design of a plant to produce 1,000 metric tons/year of silicon. Fixed capital investment estimate for the plant is $12.47 million (1975 dollars) ($17.47 million, 1980 dollars). Product cost without profit is 8.63 $/kg of silicon (1975 dollars)(12.1 $/kg, 1980 dollars).

Li, K. Y.↗
NASA NTRS1979

LSA Large Area Silicon Sheet Task Enhanced I.D. Slicing Technology for Silicon Ingots

Development of inside diameter slicing technology to significantly increase the number of useable slices per inch of crystal over industry practice is discussed. The required reduction of both blade and slice thickness is to be accomplished by a combination of three key elements of slicing technology: (1) ingot rotation with minimum exposed blade area; (2) dynamic cutting edge control; and (3) the use of prefabricated insert blades. Design modifications on a slicing saw with microprocessor controls and hardware fabrication to complete this conversion were initiated. Several runs were conducted on the engineering saw incorporating the method of ingot rotation. Ingots with diameters up to six inches were sliced successfully on a production saw.

Walters, D.↗
NASA NTRS1979

Phase 2 of the Array Automated Assembly Task for the Low Cost Solar Array Project

Two process specifications supplied by contractors were tested. The aluminum silk screening process resulted in cells comparable to those from sputtered Al. The electroless plating of contacts specification could be used only with extensive modification. Several experiments suggest that there is some degradation of the front junction during the Al back surface field (BSF) fabrication. A revised process sequence was defined which incorporates Al BSF formation. A cost analysis of this process yielded a selling price of $0.75/watt peak in 1980.

Campbell, R. B.↗
NASA NTRS1978

The Automated Array Assembly Task of the Low-cost Silicon Solar Array Project, Phase 2

An advanced process sequence for manufacturing high efficiency solar cells and modules in a cost-effective manner is discussed. Emphasis is on process simplicity and minimizing consumed materials. The process sequence incorporates texture etching, plasma processes for damage removal and patterning, ion implantation, low pressure silicon nitride deposition, and plated metal. A reliable module design is presented. Specific process step developments are given. A detailed cost analysis was performed to indicate future areas of fruitful cost reduction effort. Recommendations for advanced investigations are included.

Coleman, M. G.↗
NASA NTRS1979

Design, processing and testing of LSI arrays, hybrid microelectronics task

Mathematical cost models previously developed for hybrid microelectronic subsystems were refined and expanded. Rework terms related to substrate fabrication, nonrecurring developmental and manufacturing operations, and prototype production are included. Sample computer programs were written to demonstrate hybrid microelectric applications of these cost models. Computer programs were generated to calculate and analyze values for the total microelectronics costs. Large scale integrated (LST) chips utilizing tape chip carrier technology were studied. The feasibility of interconnecting arrays of LSU chips utilizing tape chip carrier and semiautomatic wire bonding technology was demonstrated.

Himmel, R. P.↗
NASA NTRS1979

Effect of noise spectra and a listening task upon passenger annoyance in a helicopter interior noise environment

The effects of helicopter interior noise on passenger annoyance were studied. Both reverie and listening situations were studied as well as the relative effectiveness of several descriptors (i.e., overall sound pressure level, A-weighted sound pressure level, and speech interference level) for quantifying annoyance response for these situations. The noise stimuli were based upon recordings of the interior noise of a civil helicopter research aircraft. These noises were presented at levels ranging from approximately 68 to 86 dB(A) with various gear clash tones selectively attenuated to give a range of spectra. Results indicated that annoyance during a listening condition is generally higher than annoyance during a reverie condition for corresponding interior noise environments. Attenuation of the planetary gear clash tone results in increases in listening performance but has negligible effect upon annoyance for a given noise level. The noise descriptor most effective for estimating annoyance response under conditions of reverie and listening situations is shown to be the A-weighted sound pressure level.

Clevenson, S. A.↗
NASA NTRS1979

Very high speed processing: Applicability of peripheral devices to pixel-dependent tasks

Early options studied in the satisfaction of LACIE implementation computational demands are described as well as the ultimate selection and development of an array processing solution to the problem. The economic justification, as a function of required LANDSAT analysis, is provided. The suitability of such processors for LACIE and other applications is discussed.

Lyon, J. C.↗
NASA NTRS1979

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

Jones, G. T.↗
NASA NTRS1979

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Fleming, J. R.↗
NASA NTRS1979

Phase 2: Array automated assembly task low cost silicon solar array project

Several microwave systems for use in solar cell fabrication were developed and experimentally tested. The first system used a standing wave rectangular waveguide horn applicator. Satisfactory results were achieved with this system for impedance matching and wafer surface heating uniformity. The second system utilized a resonant TM sub 011 mode cylindrical cavity but could not be employed due to its poor energy coupling efficiency. The third and fourth microwave systems utilized a circular waveguide operating in the TM sub 01 and TM sub 11 but had problems with impedance matching, efficiency, and field uniformity.

Jones, G. T.↗