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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,405 records · Page 78
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

Investigations into the Power MOSFET SEGR Phenomenon and its Physical Mechanism

The state of understanding of the destructive SEGR event in power MOSFETs is relatively mature with large published efforts, both experimental and theoretical. However, gasps remain in the uderstanding of the phenomenon, including unexplained anomalies, emperical-only dependencies on some important device and incident ion physical parameters, and limited insight into latent effets.

MOSFET SEGR↗
NASA NTRS1995

Trends in Device SEE Susceptibility from Heavy Ions

The sixth set of heavy ion single event effects (SEE) test data have been collected since the last IEEE publications in December issues of IEEE - Nuclear Science Transactions for 1985, 1987, 1989, 1991, and the IEEE Workshop Record, 1993. Trends in SEE susceptibility (including soft errors and latchup) for state-of- are evaluated.

single event effects latchup radiation hardening↗
NASA NTRS1994

Total Dose Effects in Conventional Bipolar Transistors

This paper examines various factors in bipolar device construction and design, and discusses their impact on radiation hardness. The intent of the paper is to improve understanding of the underlying mechanisms for practical devices without special test structures, and to provide (1) guidance in ways to select transistor designs that are more resistant to radiation damage, and (2) methods to estimate the maximum amount of damage that might be expected from a basic transistor design. The latter factor is extremely important in assessing the risk that future lots of devices will be substantially below design limits, which are usually based on test data for older devices.

Bipolar Devices Cassini Ionizing radiation effects↗
NASA NTRS1994

A New Class of Single Event Hard Errors

This paper reports on hard errors induced by single ions in dynamic memories. For ions with atomic number below 80, hard errors in DRAMs appear to be similar to the hard errors reported in previous work on SRAMs. One feature of these hard errors is that they tend to recover gradually with time, because of annealing, and are thus partially recoverable. However, for gold ions, a second type of hard error was discovered which is not recoverable, and appears to be due to catastrophic internal shorting rather than small changes in leakage current. Thus, nonrecoverable errors will likely occur even in devices which eliminate the extreme sensitivity to leakage current that is inherent in 4-T SRAMs and DRAMs. It is important to understand the mechanism that is responsible for nonrecoverable errors, and investigate the effect of device scaling.

single event hard errors DRAM SRAM ions gold ions ↗
NASA NTRS2002

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

flash memory program disturb wearout erase fail re↗
NASA NTRS2002

SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

FPGA Virtex II SEU↗
NASA NTRS1998

Observations on the Presumed LET Dependence of SEGR

Single-event gate rupture (SEGR)in vertical power MOSFETs is induced by charge deposited in the epitaxial region (below the gate oxide) in concert with the weakening of the oxide, both are a result of the ion passage.

Single-event gate rupture SEGR vertical power MOSF↗