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NASA NTRSDate not supplied

Spacesuit Reach Capability and Work Volume Assessment

Work volumes and reach envelopes define the locations where work objects or interfaces can be placed around a person to reduce ergonomic risk. Spacesuits, however, show unique reach patterns, due to the stiffness and mechanical constraints from pressurization. This study measured the reach motion patterns and capabilities from subjects wearing a pressurized spacesuit using a 3D motion capture system. The subjects performed arm and hand motions, focusing on extreme lateral and vertical positions. These motions defined the maximum ranges. They also performed on-suit reaches to measure where they could or couldn’t reach on the suit surface to determine where critical controls and devices could be placed on the suit. A parametric model of the reach volume was statistically built using the collected hand position data. The observed shape and size of the work volume substantially vary by persons, depending on anthropometry and strength capability. It was also indicated that the traditional metrics (e.g., simple spherical or cylindrical representations) estimated from “unsuited” persons or computer simulations may not accurately capture such variations. The results of this study can help to design and optimize space hardware and task activities, to protect crewmembers from overexertion or injuries.

Han Kim↗

NASA NTRS1993

A transient FETI methodology for large-scale parallel implicit computations in structural mechanics, part 2

Explicit codes are often used to simulate the nonlinear dynamics of large-scale structural systems, even for low frequency response, because the storage and CPU requirements entailed by the repeated factorizations traditionally found in implicit codes rapidly overwhelm the available computing resources. With the advent of parallel processing, this trend is accelerating because explicit schemes are also easier to parallellize than implicit ones. However, the time step restriction imposed by the Courant stability condition on all explicit schemes cannot yet and perhaps will never be offset by the speed of parallel hardware. Therefore, it is essential to develop efficient and robust alternatives to direct methods that are also amenable to massively parallel processing because implicit codes using unconditionally stable time-integration algorithms are computationally more efficient than explicit codes when simulating low-frequency dynamics. Here we present a domain decomposition method for implicit schemes that requires significantly less storage than factorization algorithms, that is several times faster than other popular direct and iterative methods, that can be easily implemented on both shared and local memory parallel processors, and that is both computationally and communication-wise efficient. The proposed transient domain decomposition method is an extension of the method of Finite Element Tearing and Interconnecting (FETI) developed by Farhat and Roux for the solution of static problems. Serial and parallel performance results on the CRAY Y-MP/8 and the iPSC-860/128 systems are reported and analyzed for realistic structural dynamics problems. These results establish the superiority of the FETI method over both the serial/parallel conjugate gradient algorithm with diagonal scaling and the serial/parallel direct method, and contrast the computational power of the iPSC-860/128 parallel processor with that of the CRAY Y-MP/8 system.

Farhat, Charbel↗

NASA NTRS1992

A transient FETI methodology for large-scale parallel implicit computations in structural mechanics

Explicit codes are often used to simulate the nonlinear dynamics of large-scale structural systems, even for low frequency response, because the storage and CPU requirements entailed by the repeated factorizations traditionally found in implicit codes rapidly overwhelm the available computing resources. With the advent of parallel processing, this trend is accelerating because explicit schemes are also easier to parallelize than implicit ones. However, the time step restriction imposed by the Courant stability condition on all explicit schemes cannot yet -- and perhaps will never -- be offset by the speed of parallel hardware. Therefore, it is essential to develop efficient and robust alternatives to direct methods that are also amenable to massively parallel processing because implicit codes using unconditionally stable time-integration algorithms are computationally more efficient when simulating low-frequency dynamics. Here we present a domain decomposition method for implicit schemes that requires significantly less storage than factorization algorithms, that is several times faster than other popular direct and iterative methods, that can be easily implemented on both shared and local memory parallel processors, and that is both computationally and communication-wise efficient. The proposed transient domain decomposition method is an extension of the method of Finite Element Tearing and Interconnecting (FETI) developed by Farhat and Roux for the solution of static problems. Serial and parallel performance results on the CRAY Y-MP/8 and the iPSC-860/128 systems are reported and analyzed for realistic structural dynamics problems. These results establish the superiority of the FETI method over both the serial/parallel conjugate gradient algorithm with diagonal scaling and the serial/parallel direct method, and contrast the computational power of the iPSC-860/128 parallel processor with that of the CRAY Y-MP/8 system.

Farhat, Charbel↗

NASA NTRSDate not supplied

PRELIMINARY JPSS-3 VIIRS POLARIZATION SENSITIVITY AND COMPARISON WITH S-NPP, JPSS-1 AND -2

The Visible-Infrared Imaging Radiometer Suite (VIIRS) was first launched on-board the Suomi National Polar-orbiting Partnership (S-NPP) spacecraft in October of 2011. There have been three subsequent builds of the VIIRS sensor for the Joint Polar Satellite System (JPSS) program with JPSS-1, -2 and -3 having launch dates of November 2017, March 2022 and 2026 respectively. There is also a JPSS-4 VIIRS, that is in hardware integration during 2020, with a launch date of 2031. VIIRS has 22 bands: 7 thermal emissive bands (TEBs), 14 reflective solar bands (RSBs) and a Day Night Band (DNB). Ocean Color/Chlorophyll (OCC) products use calibrated Science Data Records (SDRs) for bands M1-M7(0.412-0.865μm) to compute their ocean chemistry products. These bands require accurate polarization sensitivity characterization to compensate for polarized upwelling Rayleigh scatter and produce accurate OCC Environment Data Products (EDRs). VIIRS polarization sensitivity requirement failures have driven hardware modifications to the bandpass filters and dichroic beam splitter over the program. This paper will discuss the preliminary JPSS-3 polarization results and how these hardware modifications, as the JPSS program progresses, have affected the sensor performance. Comparisons of the polarization sensitivities between sensor builds will be discussed along with the hardware modifications that contributed to their differences.

VIIRS↗

NASA NTRSDate not supplied

Preliminary JPSS-3 VIIRS Polarization Sensitivity and Comparison with S-NPP, JPSS-1 and -2

The Visible-Infrared Imaging Radiometer Suite (VIIRS) was first launched on-board the Suomi National Polar-orbiting Partnership (S-NPP) spacecraft in October of 2011. There have been three subsequent builds of the VIIRS sensor for the Joint Polar Satellite System (JPSS) program with JPSS-1, -2 and -3 having launch dates of November 2017, March 2022 and 2026 respectively. There is also a JPSS-4 VIIRS, that is in hardware integration during 2020, with a launch date of 2031. VIIRS has 22 bands: 7 thermal emissive bands (TEBs), 14 reflective solar bands (RSBs) and a Day Night Band (DNB). Ocean Color/Chlorophyll (OCC) products use calibrated Science Data Records (SDRs) for bands M1-M7 (0.412-0.865μm) to compute their ocean chemistry products. These bands require accurate polarization sensitivity characterization to compensate for polarized upwelling Rayleigh scatter and produce accurate OCC Environment Data Products (EDRs). VIIRS polarization sensitivity requirement failures have driven hardware modifications to the bandpass filters and dichroic beam splitter over the program. This paper will discuss the preliminary JPSS-3 polarization results and how these hardware modifications, as the JPSS program progresses, have affected the sensor performance. Comparisons of the polarization sensitivities between sensor builds will be discussed along with the hardware modifications that contributed to their differences.

VIIRS↗

NASA NTRS1991

Onboard navigation rendezvous expert system

The Onboard Navigation rendezvous expert system is designed to aid the ground flight controller in monitoring the shuttle onboard navigation system. The system is designed to keep track of the navigation sensors and relative state vectors. In addition, the system also keeps an event log and fills out forms usually handled by the flight controller. This expert system is one of the few rendezvous specific systems being developed for the Mission Control Center. The expert system has been in development for six years. Through these years the system has seen hardware, software, and personnel changes. Initial development was done by the Information Systems Directorate (ISD) and Mission Operations Directorate (MOD) at Johnson Space Center. As of October 1, 1991 the system has been turned over to MOD. The system is completely developed except for some minor adjustments to the user interface. The rule base is in the verification stage with total certification of the system due to be completed by May 1992. Test cases for verification are obtained by saving data used for flight controller integrated simulations. The actual data comes from both the shuttle mission simulator and the Mission Control Center Computer. So far no actual flight data has been available. This paper covers all aspects of the system from the development history to the current hardware, software, and use of the system.

Kocen, Michelle↗

NASA NTRS2011

Hardware Testing and Implementation of RapidIO Protocol on the ISAAC iBoard for Use in the NEXUS Testbed

I am assisting the NEXUS (NEXtbUS) and ISAAC (Instrument ShAred Artifact for Computing) teams in achieving a highly reusable, highly configurable FPGA (Field Programmable Gate Array) system which uses a unified, high-speed bus standard. One of my tasks is to verify that all new ISAAC iBoards features are functioning as expected by using my previous builds to test these features and resolving any errors found. My other task is to investigate and implement the RapidIO protocol and to implement it onto the new ISAAC iBoards to be used in the NEXUS testbed. Completing these tasks will demonstrate the potential of both NEXUS and ISAAC technology. This will allow others to see the power in making use of a unified, modular system.

RapidIO Protocol↗

NASA NTRS2013

Low-Cost Space Hardware and Software

The goal of this project is to demonstrate and support the overall vision of NASA's Rocket University (RocketU) through the design of an electrical power system (EPS) monitor for implementation on RUBICS (Rocket University Broad Initiatives CubeSat), through the support for the CHREC (Center for High-Performance Reconfigurable Computing) Space Processor, and through FPGA (Field Programmable Gate Array) design. RocketU will continue to provide low-cost innovations even with continuous cuts to the budget.

hardware↗

NASA NTRSDate not supplied

Autonomous In-space Construction, Maintenance, and Reconfiguration Using Programmable Meta-Material

NASA ARC's Coded Structures Laboratory (CSL) is developing autonomous construction, maintenance, and reconfiguration technologies to meet long-duration and deep space infrastructure needs, in accordance with long-term NASA goals of "in-space reliance" and "mass-less exploration." We seek to achieve these capabilities by utilizing a "programmable meta-material" approach that integrates emerging advances in materials (mechanical meta-materials), manufacturing (cooperative mobile robotics), and autonomy (multi-agent planning algorithms). Through the ARMADAS project, we have shown assembly of high-performance engineered cellular materials using multiple cooperating mobile robotic assemblers. In this paper, we describe how such a programmable meta-material architecture may shift the paradigm of how we design, build, manufacture, and operate future space infrastructure and assets. The core of a programmable meta-material architecture consists of 3 main technology sub-areas: the structure, the assembly agents, and the assembly algorithms. We co-design these systems to ensure an adaptable system that can create and reconfigure structures from a base set of building block components. From this core technology, we can branch out and expand the capability of the system through additional secondary component types and robotic agents to perform activities such as inspections, maintenance, repair, payload installation, or perform power and communications interconnect. As these technologies mature, future designers will be able to utilize the system to rapidly integrate and operate assets in space or on planetary surfaces from a set of well-tested part library, or create their own modules to integrate into the system. A core trait to the development of this system is the automation approach. Because of the modular and functional discrete (pixel-like) nature of the structural system, a diverse set of powerful algorithms for analysis, planning, and simulation can be adapted and leveraged to optimize construction, maintenance, and dynamic reorganization (as hardware with programmable form and function). With an ability to free the design space from launch vehicle constraints and fundamentally shift how a mission is designed and conducted, we discuss the influence of a programmable meta-material architecture on mission design, build, and operations. For the "design phase", we discuss project lifecycle effects, costs, time, and performance. For the "build phase", we discuss reusability, ISRU, manufacturing, material logistics, and scalability. And for "operations", we discuss autonomy, maintenance and upgrades, reliability, and reconfiguration. Autonomy and modularity are the primary enabling traits of this system. Engineering systems that utilize a modular and reconfiguration building block approach such as digital communication and computation systems, currently lead all other areas of technology in size and complexity scalability. NASA is extending the benefits and flexibility of digital systems to hardware systems, to optimize materials lifecycle management and expand our space exploration mission capabilities.

in space assembly↗

NASA NTRS2001

The Automatic Parallelisation of Scientific Application Codes Using a Computer Aided Parallelisation Toolkit

The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. Historically, the lack of a programming standard for using directives and the rather limited performance due to scalability have affected the take-up of this programming model approach. Significant progress has been made in hardware and software technologies, as a result the performance of parallel programs with compiler directives has also made improvements. The introduction of an industrial standard for shared-memory programming with directives, OpenMP, has also addressed the issue of portability. In this study, we have extended the computer aided parallelization toolkit (developed at the University of Greenwich), to automatically generate OpenMP based parallel programs with nominal user assistance. We outline the way in which loop types are categorized and how efficient OpenMP directives can be defined and placed using the in-depth interprocedural analysis that is carried out by the toolkit. We also discuss the application of the toolkit on the NAS Parallel Benchmarks and a number of real-world application codes. This work not only demonstrates the great potential of using the toolkit to quickly parallelize serial programs but also the good performance achievable on up to 300 processors for hybrid message passing and directive-based parallelizations.

Ierotheou, C.↗

NASA NTRS1977

NASA standard communications and data handling subsystem

The paper gives a functional description and discusses hardware implementation for the Communication and Data Handling (C&DH) subsystem of the Multimission Modular Spacecraft. The C&DH subsystem: (1) provides the command and telemetry link between the spacecraft and the terrestrial system, (2) distributes commands to and collects telemetry from all spacecraft systems via a duplex serial multiplex data bus and remote interface units, and (3) contains onboard computation capability. The C&DH is a single 4 x 4 x 1-1/2 foot module; the stuffed module weighs 270 lbs including 60 lbs of mission unique weight. The hardware is versatile and cost effective, and its modular structure permits repair, refurbishment, and even modification/updating in space

Robinson, D. L.↗

NASA NTRS2005

Structural Analysis Made 'NESSUSary'

Everywhere you look, chances are something that was designed and tested by a computer will be in plain view. Computers are now utilized to design and test just about everything imaginable, from automobiles and airplanes to bridges and boats, and elevators and escalators to streets and skyscrapers. Computer-design engineering first emerged in the 1970s, in the automobile and aerospace industries. Since computers were in their infancy, however, architects and engineers during the time were limited to producing only designs similar to hand-drafted drawings. (At the end of 1970s, a typical computer-aided design system was a 16-bit minicomputer with a price tag of $125,000.) Eventually, computers became more affordable and related software became more sophisticated, offering designers the "bells and whistles" to go beyond the limits of basic drafting and rendering, and venture into more skillful applications. One of the major advancements was the ability to test the objects being designed for the probability of failure. This advancement was especially important for the aerospace industry, where complicated and expensive structures are designed. The ability to perform reliability and risk assessment without using extensive hardware testing is critical to design and certification. In 1984, NASA initiated the Probabilistic Structural Analysis Methods (PSAM) project at Glenn Research Center to develop analysis methods and computer programs for the probabilistic structural analysis of select engine components for current Space Shuttle and future space propulsion systems. NASA envisioned that these methods and computational tools would play a critical role in establishing increased system performance and durability, and assist in structural system qualification and certification. Not only was the PSAM project beneficial to aerospace, it paved the way for a commercial risk- probability tool that is evaluating risks in diverse, down- to-Earth application

Source record↗

NASA NTRS1989

Queuing theory models for computer networks

A set of simple queuing theory models which can model the average response of a network of computers to a given traffic load has been implemented using a spreadsheet. The impact of variations in traffic patterns and intensities, channel capacities, and message protocols can be assessed using them because of the lack of fine detail in the network traffic rates, traffic patterns, and the hardware used to implement the networks. A sample use of the models applied to a realistic problem is included in appendix A. Appendix B provides a glossary of terms used in this paper. This Ames Research Center computer communication network is an evolving network of local area networks (LANs) connected via gateways and high-speed backbone communication channels. Intelligent planning of expansion and improvement requires understanding the behavior of the individual LANs as well as the collection of networks as a whole.

Galant, David C.↗

NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗

NASA NTRSDate not supplied

A Multi-Architecture Approach for Implicit Computational Fluid Dynamics on Unstructured Grids

High-performance computing (HPC) architectures are trending toward manycore paradigms such as graphics processing units (GPUs). Approximately half of the top 100 publicly disclosed supercomputers in the world utilize GPU accelerators for performance. This is in contrast to a decade ago, where there were only a few such machines in the top 100. It is not currently possible to compile and run legacy central processing unit (CPU) software efficiently on GPUs without significant refactoring. Though a number of frameworks offering performance portability exist, none offer a standardized specification that is supported by all major hardware vendors. Additionally, experiences show that obtaining a high percentage of peak performance often requires architecture-specific code. This work details a pragmatic multi-architecture computational fluid dynamics library focused on aerospace problems across the speed range from low subsonic to hypersonic flows involving thermochemical nonequilibrium. A thin abstraction layer above NVIDIA CUDA C++ is utilized, which enables primarily single-source software currently capable of running efficiently on multicore CPUs, NVIDIA GPUs, AMD GPUs, and Intel GPUs. Results on various problems of interest across the speed range are presented and performance is compared between various architectures.

GPU↗

NASA NTRSDate not supplied

A Multi-Architecture Approach for Implicit Computational Fluid Dynamics on Unstructured Grids

GPU↗

NASA NTRS2004

Improved Timing Scheme for Spaceborne Precipitation Radar

An improved timing scheme has been conceived for operation of a scanning satellite-borne rain-measuring radar system. The scheme allows a real-time-generated solution, which is required for auto targeting. The current timing scheme used in radar satellites involves pre-computing a solution that allows the instrument to catch all transmitted pulses without transmitting and receiving at the same time. Satellite altitude requires many pulses in flight at any time, and the timing solution to prevent transmit and receive operations from colliding is usually found iteratively. The proposed satellite has a large number of scanning beams each with a different range to target and few pulses per beam. Furthermore, the satellite will be self-targeting, so the selection of which beams are used will change from sweep to sweep. The proposed timing solution guarantees no echo collisions, can be generated using simple FPGA-based hardware in real time, and can be mathematically shown to deliver the maximum number of pulses per second, given the timing constraints. The timing solution is computed every sweep, and consists of three phases: (1) a build-up phase, (2) a feedback phase, and (3) a build-down phase. Before the build-up phase can begin, the beams to be transmitted are sorted in numerical order. The numerical order of the beams is also the order from shortest range to longest range. Sorting the list guarantees no pulse collisions. The build-up phase begins by transmitting the first pulse from the first beam on the list. Transmission of this pulse starts a delay counter, which stores the beam number and the time delay to the beginning of the receive window for that beam. The timing generator waits just long enough to complete the transmit pulse plus one receive window, then sends out the second pulse. The second pulse starts a second delay counter, which stores its beam number and time delay. This process continues until an output from the first timer indicates there is less than one transmit pulse width until the start of the next receive event. This blocks future transmit pulses in the build-up phase. The feedback phase begins with the first timer paying off and starting the first receive window. When the first receive window is complete, the timing generator transmits the next beam from the list. When the second timer pays off, the second receive event is started. Following the second receive event, the timing generator will transmit the next beam on the list and start an additional timer. The timers work in a circular buffer fashion so there only need to be enough to cover the maximum number of echoes in flight.

Berkun, Andrew↗

NASA NTRS2017

Performance Enhancement of a Computational Persistent Homology Package

In recent years, persistent homology has become an attractive method for data analysis. It captures topological features, such as connected components, holes, voids, etc., from a point cloud by finding out when these features appear and disappear in the filtration sequence. In this project, we focus on improving the performance of Eirene, a fancy computational persistent homology package. Eirene is a 5000-line opensource software implemented by using the dynamic programming language Julia. We use the Julia profiling tools to identify the performance bottlenecks and develop different methods to manage the bottlenecks, including the parallelization of some time-consuming functions on the multicore/manycore hardware. The empirical results show that the performance can be greatly improved.

Profiling↗