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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,387 records · Page 77
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

Niedra, Janis M.↗
NASA NTRS2007

Fabrication of a Thermally Isolated and Pre-amplified Transistor Module with Polyimide Micro-wires for Cryogenic Detectors

For use in cryogenic applications such as bolometer and x-ray microcalorimeter arrays, pre-amplifying Junction Field Effect Transistors (JFETs) are often required for the readout electronics. The optimum operating temperature of the JFETs is 130 Kelvin while the cryogenic detectors operate in the milli-Kelvin range. Thus, the JFETs must be heated up but thermally isolated from the surrounding cryogenic instruments. In the past, the thermal isolation was accomplished by suspending the JFETs with low conductance wires such as manganium or stainless steel on a Kevlar support platform [I]. This also achieved electrical connections. However, this assembly required manual soldering work, which could raise a reliability issue for the cryogenic applications. In order to eliminate the manual work, polyimide micro-wires were developed [2]. The wires must be of sufficient length to decrease the heat load and in tension to prevent microphonic noise from vibration of the wires: the polyimide wires were patterned into llS"shaped curves over a thin metal wires such as aluminum, titanium, or niobium. The bilayer of the films were then suspended by etching silicon substrate thus to make freestanding air bridges (enough explanation?). In this paper, we present a method to fabricate micromachined JFET mechanical modules suspended by polyimide Pyraline micro-wires and heated up with built-in aluminum micro-heaters.

Oh, L. H.↗
NASA NTRS1983

Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques

A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

Policastro, Steven G.↗
NASA NTRS2007

Flexible carbon-based ohmic contacts for organic transistors

The present invention relates to a system and method of organic thin-film transistors (OTFTs). More specifically, the present invention relates to employing a flexible, conductive particle-polymer composite material for ohmic contacts (i.e. drain and source).

Brandon, Erik↗
NASA NTRS2004

Evolutionary Multiobjective Design Targeting a Field Programmable Transistor Array

This paper introduces the ISPAES algorithm for circuit design targeting a Field Programmable Transistor Array (FPTA). The use of evolutionary algorithms is common in circuit design problems, where a single fitness function drives the evolution process. Frequently, the design problem is subject to several goals or operating constraints, thus, designing a suitable fitness function catching all requirements becomes an issue. Such a problem is amenable for multi-objective optimization, however, evolutionary algorithms lack an inherent mechanism for constraint handling. This paper introduces ISPAES, an evolutionary optimization algorithm enhanced with a constraint handling technique. Several design problems targeting a FPTA show the potential of our approach.

global optimization↗
NASA NTRS2009

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

Radisic, Vesna↗
NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗
NASA NTRS2009

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

MacLeod, Todd C.↗
NASA NTRS2011

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Hunt, Mitchell↗
NASA NTRS2005

Flexible, Carbon-Based Ohmic Contacts for Organic Transistors

A low-temperature process for fabricating flexible, ohmic contacts for use in organic thin-film transistors (OTFTs) has been developed. Typical drainsource contact materials used previously for OTFTs include (1) vacuum-deposited noble-metal contacts and (2) solution-deposited intrinsically conducting molecular or polymeric contacts. Both of these approaches, however, have serious drawbacks.

Brandon, Erik↗
NASA NTRS2012

I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

Laws, Crystal↗
NASA NTRS2012

Effects of Radiation and Long-Term Thermal Cycling on EPC 1001 Gallium Nitride Transistors

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Data obtained on long-term thermal cycling of new un-irradiated and irradiated samples of EPC1001 gallium nitride enhancement-mode transistors are presented. This work was done by a collaborative effort including GRC, GSFC, and support the NASA www.nasa.gov 1 JPL in of Electronic Parts and Packaging (NEPP) Program

Patterson, Richard L.↗
NASA NTRS2012

Evaluation of Enhanced Low Dose Rate Sensitivity in Discrete Bipolar Junction Transistors

We evaluate the low dose rate sensitivity in several families of discrete bipolar transistors across device parameter, quality assurance level, and irradiation bias configuration. The 2N2222 showed the most significant low dose rate sensitivity, with low dose rate enhancement factor of 3.91 after 100 krad(Si). The 2N2907 also showed critical degradation levels. The devices irradiated at 10 mrad(Si)/s exceeded specifications after 40 and 50 krad(Si) for the 2N2222 and 2N2907 devices, respectively.

Chen, Dakai↗
NASA NTRS2013

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Hunt, Mitchell↗
NASA NTRS2011

Dose Rate Effects in Linear Bipolar Transistors

Dose rate effects are examined in linear bipolar transistors at high and low dose rates. At high dose rates, approximately 50% of the damage anneals at room temperature, even though these devices exhibit enhanced damage at low dose rate. The unexpected recovery of a significant fraction of the damage after tests at high dose rate requires changes in existing test standards. Tests at low temperature with a one-second radiation pulse width show that damage continues to increase for more than 3000 seconds afterward, consistent with predictions of the CTRW model for oxides with a thickness of 700 nm.

linear integrated circuit↗