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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,351 records · Page 75

Differences in total stem value when merchandizing with a tracked processor versus a knuckle–boom loader in Pinus taeda

Using tracked processors over knuckle–boom loaders to increase total value per tree when merchandizing timber on the landing has become a topic of interest in the southeastern region of the United States. This study compared merchantability values, product classes, and product weights of loblolly pine (Pinus taeda) for both machines to determine if there was a significant difference between machines when processing the same tree. In order to process the same tree twice, the chains from the tracked processor had to be removed from the bottom saw bar. This allowed the processor to simulate the merchandising process without actually marking or cutting the tree for a more realistic comparison. Data were analyzed using paired t–tests and two–way ANOVA models. Results depicted that when diameter and total lengths are visually estimated by the knuckle–boom loader. A significant difference in value occurs, however, once diameter and total length are modified to match the tracked processors for more accurate measurements, no difference in value was seen. Here, these results demonstrate that until mill specifications become more stringent, there is little incentive for loggers to purchase a tracked processor if their only motivation is to increase merchantability values.

42 ENGINEERING↗

Thermophysical properties of FLiBe using moment tensor potentials

Fluoride salts are prospective materials for applications in some next-generation nuclear reactors and their thermophysical properties at various conditions are of interest. Experimental measurement of the properties of these salts is often difficult and, in some cases, unfeasible due to challenges from high temperatures, impurity control, and corrosivity. Therefore, accurate theoretical methods are needed for fluoride salt property prediction. In this work, we used moment tensor potentials (MTP) to approximate the potential energy surface of eutectic FLiBe (66.6% LiF – 33.3% BeF2) predicted by the ab initio (DFT-D3) method. Here, we then used the developed potential and molecular dynamics to obtain several thermophysical properties of FLiBe, including radial distribution functions, density, self-diffusion coefficients, thermal expansion, specific heat capacity, bulk modulus, viscosity, and thermal conductivity. Our results show that the MTP potential approximates the potential energy surface accurately and the overall approach yields very good agreement with experimental values. The converged fitting can be obtained with less than 600 configurations generated from DFT calculations, which data can be generated in just 1200 core hours on today's typical processors. The MTP potential is faster than many machine learning potentials and about one order of magnitude slower than widely used empirical molten salt potentials such as Tosi/Fumi.

36 MATERIALS SCIENCE↗

P4: Portable Parallel Processing Pipelines for Interactive Information Visualization

We present P4, an information visualization toolkit that combines declarative design specification and GPU computing for building high-performance interactive systems. Most of the existing information visualization toolkits do not harness the power of parallel processors in today's mainstream computers. P4 leverages GPU computing to accelerate both data processing and visualization rendering for interactive visualization applications. P4's programming interface offers a declarative visualization grammar for rapid specifications of data transformations, visual encodings, and interactions. By simplifying the development of GPU-accelerated visualization systems while supporting a high degree of flexibility and customization for design specification, P4 narrows the gap between expressiveness and scalability in information visualization toolkits. Through a range of examples and benchmark tests, we demonstrate that P4 provides high efficiency for creating interactive visualizations and offers drastic performance improvement over current state-of-the-art toolkits.

97 MATHEMATICS AND COMPUTING↗

HipGISAXS

Implementation of a flexible Grazing Incidence Small-Angle Scattering (GISAXS). Simulation code based on the Distorted Wave Born Approximation (DWBA) theory that effectively utilizes the parallel processing power provided by graphic processors and multicore processors. This constitutes a handy tool for experimentalists facing a massive flux of data, allowing them to accurately simulate the GISAXS process and analyze the produced data. The software computes the diffraction image for any given super position of custom shapes or morphologies in a user-defined region of the reciprocal space for all possible grazing incidence angles and in-plane sample rotations. This flexibility then allows to easily tackle a wide range of possible sample structures such as nanoparticles o top of or embedded in a substrate or a multilayered structure. In cases where the sample displays regions of significant refractive index contrast, an algorithm has been implemented to perform a slicing of the sample along the vertical direction and compute the averaging refractive index profile to be used as the reference geometry of the unpertubed system. Preliminary tests show good agreement with experimental data for a variety of commonly encountered nanostructures.

Xiaoye, Sherry Li↗

Emulating the Android Boot Process

Critical vulnerabilities continue to be discovered in the boot process of Android smartphones used around the world. The entire device's security is compromised if boot security is compromised, so any weakness presents undue risk to users. Vulnerabilities persist, in part, because independent security analysts lack access and appropriate tools. In response to this gap, we implemented a procedure for emulating the early phase of the Android boot process. This work demonstrated feasibility and utility of emulation in this space. By using HALucinator, we derived execution context and data flow, as well as incorporated peripheral hardware behavior. While smartphones with shared processors have substantial code overlap regardless of vendor, generational changes can have a significant impact. By applying our approach to older and modern devices, we learned interesting characteristics about the system. Such capabilities introduce new levels of introspection and operation understanding not previously available to mobile researchers.

97 MATHEMATICS AND COMPUTING↗

Crew procedures development techniques

The study developed requirements, designed, developed, checked out and demonstrated the Procedures Generation Program (PGP). The PGP is a digital computer program which provides a computerized means of developing flight crew procedures based on crew action in the shuttle procedures simulator. In addition, it provides a real time display of procedures, difference procedures, performance data and performance evaluation data. Reconstruction of displays is possible post-run. Data may be copied, stored on magnetic tape and transferred to the document processor for editing and documentation distribution.

Arbet, J. D.↗

Microprocessor-to-system/370 interface

The design and operation of a microprocessor interface unit which allows use of a computer terminal for communication at 110 or 300 baud both with a central host computer and with the microprocessor monitor are documented. Additionally, the interface permits the host computer to load the microprocessor memory directly with object code, avoiding the use of intermediate data storage such as paper tape. The central computer, containing an assembler language processor for the target microcomputer, can be used from the terminal with all the flexibility offered by the virtual machine facility, producing object code for the micro plus program listings and supporting outputs. The object code can then be loaded directly to the micro and the same terminal device used to run the micro program, communicating with the micro's monitor routine.

Lilley, R. W.↗

A user oriented microcomputer facility for designing linear quadratic Gaussian feedback compensators

A laboratory design facility for digital microprocessor implementation of linear-quadratic-Gaussian feedback compensators is described. Outputs from user interactive programs for solving infinite time horizon LQ regulator and Kalman filter problems were conditioned for implementation on the laboratory microcomputer system. The software consisted of two parts: an offline high-level program for solving the LQ Ricatti equations and generating associated feedback and filter gains and a cross compiler/macro assembler which generates object code for the target microprocessor system. A PDP 11/70 with a UNIX operating system was used for all high level program and data management, and the target microprocessor system is an Intel MDS (8080-based processor). Application to the control of a two dimensional inverted pendulum is presented and issues in expanding the design/prototyping system to other target machine architectures are discussed.

Houpt, P. K.↗

A CCD tracker for closed-loop instrument pointing at Halley's comet

An optical tracker based on CCD technology has been developed for the closed-loop pointing of the narrow-angle imaging system of the proposed Halley's comet intercept mission at the comet nucleus. The target tracker, needed to assure the accurate pointing of science instruments as the nucleus rapidly passes the spacecraft, is a component of the pointing control system, which also includes a two-axis articulated instrument platform and high-resolution optical encoders to measure platform orientation relative to spacecraft structure. The device was designed on the basis of a CCD imaging array to calculate target centroid position based on the optical intensity of all pixels containing the image, and a processor to perform spacecraft attitude control, pointing control and target tracker control and data processing functions. The tracker has been configured to operate in both target acquisition and tracking modes. Preliminary simulation results and past experiments on similar trackers indicate that excellent tracking performance can be achieved, and a breadboard version of the tracker is currently being fabricated.

Stanton, R. H.↗

Landsat hydrobiological classification for an inland fresh water marsh within Everglades National Park

The considered investigation is concerned with the application of Landsat Multispectral Scanner (MSS) data to the classification of vegetative communities and the establishment of flow vectors for the Shark River Slough in Everglades National Park, Florida. A systematic array of 'ground truth' was established utilizing comprehensive hydrologic field data and conventional high altitude infrared aerial photography. A control network was defined that represented all hydrobiological zones (those wetland vegetative communities that directly influence the rate of overland sheet flow) in the Shark River Slough. These data were then directly applied to the Landsat imagery utilizing an interactive multispectral processor which generated hydrographic maps of the slough and defined the surface radiance characteristics of each hydrobiological system. It was found that the application of Landsat imagery for hydrologic applications in a wetlands area, such as the Shark River Slough in Everglades National Park, is definitely a viable tool for resource management.

Rose, P. W.↗

Demodulator and Accumulator for the High-speed Data Acquisition System

In support of nonflight project data acquisition, a high speed data acquisition system was designed. The demodulator and accumulator modules at the heart of this system perform the detection and prefiltering of data which are then further processed by a floating point systems 5210 array processor. Block diagrams of the demodulator and accumulator modules are presented.

Brokl, S. S.↗

Feasibility study for the advanced one-dimensional high temperature optical strain measurement system, phase 3

The Instrumentation and Control Technology Division is developing optical strain measurement systems for applications using high temperature wire and fiber specimens. This feasibility study has determined that stable optical signals can be obtained from specimens at temperatures beyond 2,400 C. A system using an area array sensor is proposed to alleviate off-axis decorrelation arising from rigid body motions. A digital signal processor (DSP) is recommended to perform speckle correlations at a rate near the data acquisition rate. Design parameters are discussed, and fundamental limits on the speckle shift strain measurement technique are defined.

Lant, Christian T.↗

Front-End Processor For Metrology-Information System

Front-end processor for NASA Metrology Information System (NMIS) is real-time relational data-base computer system designed to distribute processing for NMIS mainframe system or run as stand-alone local-area-network data-base system. System used in large calibration laboratories for work control and to maintain records of calibration, repair, costs, manpower usage, traceability, and other pertinent facts about instruments supported by laboratories. Provides enhancements to existing NASA Metrology Information System and batches upload to minimize mainframe I/O at times of heavy usage.

Muse, Walter S.↗

Portable Computer Keyboard For Use With One Hand

Data-entry device held in one hand and operated with five fingers. Contains seven keys. Letters, numbers, punctuation, and cursor commands keyed into computer by pressing keys in various combinations. Device called "data egg" used where standard typewriter keyboard unusable or unavailable. Contains micro-processor and 32-Kbyte memory. Captures text and transmits it to computer. Concept extended to computer mouse. Especially useful to handicapped or bedridden people who find it difficult or impossible to operate standard keyboards.

Friedman, Gary L.↗

Highly Parallel Computing Architectures by using Arrays of Quantum-dot Cellular Automata (QCA): Opportunities, Challenges, and Recent Results

There has been significant improvement in the performance of VLSI devices, in terms of size, power consumption, and speed, in recent years and this trend may also continue for some near future. However, it is a well known fact that there are major obstacles, i.e., physical limitation of feature size reduction and ever increasing cost of foundry, that would prevent the long term continuation of this trend. This has motivated the exploration of some fundamentally new technologies that are not dependent on the conventional feature size approach. Such technologies are expected to enable scaling to continue to the ultimate level, i.e., molecular and atomistic size. Quantum computing, quantum dot-based computing, DNA based computing, biologically inspired computing, etc., are examples of such new technologies. In particular, quantum-dots based computing by using Quantum-dot Cellular Automata (QCA) has recently been intensely investigated as a promising new technology capable of offering significant improvement over conventional VLSI in terms of reduction of feature size (and hence increase in integration level), reduction of power consumption, and increase of switching speed. Quantum dot-based computing and memory in general and QCA specifically, are intriguing to NASA due to their high packing density (10(exp 11) - 10(exp 12) per square cm ) and low power consumption (no transfer of current) and potentially higher radiation tolerant. Under Revolutionary Computing Technology (RTC) Program at the NASA/JPL Center for Integrated Space Microelectronics (CISM), we have been investigating the potential applications of QCA for the space program. To this end, exploiting the intrinsic features of QCA, we have designed novel QCA-based circuits for co-planner (i.e., single layer) and compact implementation of a class of data permutation matrices, a class of interconnection networks, and a bit-serial processor. Building upon these circuits, we have developed novel algorithms and QCA-based architectures for highly parallel and systolic computation of signal/image processing applications, such as FFT and Wavelet and Wlash-Hadamard Transforms.

Fijany, Amir↗

Network-Attached Solid-State Recorder Architecture

A document discusses placing memory modules on the high-speed serial interconnect, which is used by a spacecraft s computer elements for inter-processor communications, to allow all multiple computer system architectures to access the spacecraft data storage at the same time. Each memory board is identical electrically and receives its bus ID upon connection to the system. The computer elements are configured in a similar fashion. The architecture allows for multiple memory boards to be accessed simultaneously by different computer elements, and results in a scalable, strong, fault-tolerant system. The IEEE-1393 ring bus can be routed so that multiple card failures can occur and the mass memory storage will still function.

Cox, Brian↗

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗

Development of a NASA 6-U Satellite

NASA/Wallops Flight Facility has focused on the development of new technologies for the advancement of 6 Unit (6U) small satellites. From the design of the structure and instrument support hardware to improvements in the deployer, NASA is concentrating on maximizing the potential of small satellites for the benefit of science. The telemetry system provides much higher data rates than typical I U UHF system. 6U provides up to several hundred kilobits per second and utilizes the existing NASA Ground Network for data reception. The guidance, navigation and control system keeps the satellite pointed within plus or minus 10 degrees of the sun and has knowledge of the sun vector within 1 degree. The 6U power design increased the options for different voltages and power switching capabilities and is capable of supporting instruments with higher power requirements. The Command & Data Handling (C&DH) system includes a low-power 520 MHz flight processor which provides more processing capability than existing I U processor technologies. These optimized technologies will offer the science community a greater opportunity for flying more sophisticated and complex instruments.

Thompson, Linda D.↗