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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,351 records · Page 75
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Evaluation of existing and proposed computer architectures for future ground-based systems

Parallel processing architectures and techniques used in current supercomputers are described and projections are made of future advances. Presently, the von Neumann sequential processing pattern has been accelerated by having separate I/O processors, interleaved memories, wide memories, independent functional units and pipelining. Recent supercomputers have featured single-input, multiple data stream architectures, which have different processors for performing various operations (vector or pipeline processors). Multiple input, multiple data stream machines have also been developed. Data flow techniques, wherein program instructions are activated only when data are available, are expected to play a large role in future supercomputers, along with increased parallel processor arrays. The enhanced operational speeds are essential for adequately treating data from future spacecraft remote sensing instruments such as the Thematic Mapper.

Schulbach, C.↗
NASA NTRS1985

Parallel, iterative solution of sparse linear systems - Models and architectures

Solving large, sparse, linear systems of equations is a fundamental problem in large scale scientific and engineering computation. A model of a general class of asynchronous, iterative solution methods for linear systems is developed. In the model, the system is solved by creating several cooperating tasks that each compute a portion of the solution vector. A data transfer model predicting both the probability that data must be transferred between two tasks and the amount of data to be transferred is presented. This model is used to derive an execution time model for predicting parallel execution time and an optimal number of tasks given the dimension and sparsity of the coefficient matrix and the costs of computation, synchronization, and communication. The suitability of different parallel architectures for solving randomly sparse linear systems is discussed. Based on the complexity of task scheduling, one parallel architecture, based on a broadcast bus, is presented and analyzed.

Reed, D. A.↗
NASA NTRS1986

National space transportation and support study/mission requirements and architecture studies

The government approach to fulfilling the requirements of the National Space Transportation and Support Study is described. DOD and NASA were required to determine the architecture and technology that would be needed for civil and defense space transportation during the 1995-2010 time range. NASA collected data from the National Commission on Space and the DOD research focused on SDI requirements. The objectives and recommendations of the space transportation architecture, transportation and support systems, and technology assessment and planning tasks are discussed.

Durocher, C. L.↗
NASA NTRS1987

Advanced space communications architecture study. Volume 2: Technical report

The technical feasibility and economic viability of satellite system architectures that are suitable for customer premise service (CPS) communications are investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on systems that permit low-cost user terminals. Frequency division multiple access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single-hop network interconnectivity is accomplished via downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000 W. Nonrecurring satellite cost is estimated at $110 million, with the first-unit cost at $113 million. In large quantities, the user terminal cost estimate is $25,000. For an assumed traffic profile, the required system revenue has been computed as a function of the internal rate of return (IRR) on invested capital. The equivalent user charge per-minute of 64-kbps channel service has also been determined.

Horstein, Michael↗
NASA NTRS1987

Advanced space communications architecture study. Volume 1: Executive summary

The technical feasibility and economic viability of satellite system architectures that are suitable for Customer Premise Service (CPS) communications is investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on system that permit low cost user terminals. Frequency Division Multiple Access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single hop network interconnectivity is accomplished through use of downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000W. Nonrecurring satellite cost is estimated at $110 million, with the first unit cost at $113 million. In large quantities, the user terminal cost estimate is $25,000.

Horstein, Michael↗
NASA NTRS1987

Parallel VLSI architecture emulation and the organization of APSA/MPP

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

Odonnell, John T.↗
NASA NTRS1987

The architecture of tomorrow's massively parallel computer

Goodyear Aerospace delivered the Massively Parallel Processor (MPP) to NASA/Goddard in May 1983, over three years ago. Ever since then, Goodyear has tried to look in a forward direction. There is always some debate as to which way is forward when it comes to supercomputer architecture. Improvements to the MPP's massively parallel architecture are discussed in the areas of data I/O, memory capacity, connectivity, and indirect (or local) addressing. In I/O, transfer rates up to 640 megabytes per second can be achieved. There are devices that can supply the data and accept it at this rate. The memory capacity can be increased up to 128 megabytes in the ARU and over a gigabyte in the staging memory. For connectivity, there are several different kinds of multistage networks that should be considered.

Batcher, Ken↗
NASA NTRS1987

Distributed phased array architecture study

Variations in amplifiers and phase shifters can cause degraded antenna performance, depending also on the environmental conditions and antenna array architecture. The implementation of distributed phased array hardware was studied with the aid of the DISTAR computer program as a simulation tool. This simulation provides guidance in hardware simulation. Both hard and soft failures of the amplifiers in the T/R modules are modeled. Hard failures are catastrophic: no power is transmitted to the antenna elements. Noncatastrophic or soft failures are modeled as a modified Gaussian distribution. The resulting amplitude characteristics then determine the array excitation coefficients. The phase characteristics take on a uniform distribution. Pattern characteristics such as antenna gain, half power beamwidth, mainbeam phase errors, sidelobe levels, and beam pointing errors were studied as functions of amplifier and phase shifter variations. General specifications for amplifier and phase shifter tolerances in various architecture configurations for C band and S band were determined.

Bourgeois, Brian↗
NASA NTRS1986

Architecture and performance of a real time differential GPS ground station

The NAVSTAR Global Positioning System (GPS) is a satellite based navigation system that can be operated in a differential mode. The basic concept of differential GPS is to have a local ground station at a known location. The ground station continuously determines bias corrections based on the received satellite signals and transmits these corrections to local users. This allows the user to improve significantly their estimate of position. The architecture of a real time differential GPS ground station based on two STI (Stanford Telecommunications, Inc.) single-channel GPS receivers is presented. Receiver requirements are described, together with the receiver architectures. Real time operation results are presented for recent data collected from six satellites.

Turner, R. N.↗
NASA NTRS1987

System architecture of a gallium arsenide one-gigahertz digital IC tester

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Fouts, Douglas J.↗
NASA NTRS1986

Simulation system architecture design for generic communications link

This paper addresses a computer simulation system architecture design for generic digital communications systems. It addresses the issues of an overall system architecture in order to achieve a user-friendly, efficient, and yet easily implementable simulation system. The system block diagram and its individual functional components are described in detail. Software implementation is discussed with the VAX/VMS operating system used as a target environment.

Tsang, Chit-Sang↗
NASA NTRS1987

An evaluation plan of bus architectures and protocols using the NASA Ames intelligent redundant actuation system

Means for evaluating data bus architectures and protocols for highly integrated flight control system applications are needed. Described are the criteria and plans to do this by using the NASA/Ames Intelligent Redundant Actuation System (IRAS) experimental set-up. Candidate bus architectures differ from one another in terms of: topology, access control, message transfer schemes, message characteristics, initialization. data flow control, transmission rates, fault tolerance, and time synchronization. The evaluation criteria are developed relative to these features. A preliminary, analytical evaluation of four candidate busses (MIL-STD-1553B, DATAC, Ethernet, and HSIS) is described. A bus must be exercised in a real-time environment to evaluate its dynamic characteristics. A plan for real-time evaluation of these four busses using a combination of hardware and simulation techniques is presented.

Defeo, P.↗
NASA NTRS1987

A multiprocessing architecture for real-time monitoring

A multiprocessing architecture for performing real time monitoring and analysis using knowledge-based problem solving techniques is discussed. To handle asynchronous inputs and perform in real time, the system consists of three or more separate processes which run concurrently on one or more processors and communicate via a message passing scheme. The Data Management Process gathers, compresses, scales and sends the incoming telemetry data to other tasks. The Inference Process consists of a proprietary high performance inference engine that runs at 1000 rules per second using telemetry data to perform real time analysis on the state and health of the Space Telescope. The multiprocessing architecture has been interfaced to a simulator and is able to process the incoming telemetry in real time.

Laffey, Thomas J.↗
NASA NTRS1988

Introduction to a system for implementing neural net connections on SIMD architectures

Neural networks have attracted much interest recently, and using parallel architectures to simulate neural networks is a natural and necessary application. The SIMD model of parallel computation is chosen, because systems of this type can be built with large numbers of processing elements. However, such systems are not naturally suited to generalized communication. A method is proposed that allows an implementation of neural network connections on massively parallel SIMD architectures. The key to this system is an algorithm permitting the formation of arbitrary connections between the neurons. A feature is the ability to add new connections quickly. It also has error recovery ability and is robust over a variety of network topologies. Simulations of the general connection system, and its implementation on the Connection Machine, indicate that the time and space requirements are proportional to the product of the average number of connections per neuron and the diameter of the interconnection network.

Tomboulian, Sherryl↗
NASA NTRS1988

Efficient parallel architecture for highly coupled real-time linear system applications

A systematic procedure is developed for exploiting the parallel constructs of computation in a highly coupled, linear system application. An overall top-down design approach is adopted. Differential equations governing the application under consideration are partitioned into subtasks on the basis of a data flow analysis. The interconnected task units constitute a task graph which has to be computed in every update interval. Multiprocessing concepts utilizing parallel integration algorithms are then applied for efficient task graph execution. A simple scheduling routine is developed to handle task allocation while in the multiprocessor mode. Results of simulation and scheduling are compared on the basis of standard performance indices. Processor timing diagrams are developed on the basis of program output accruing to an optimal set of processors. Basic architectural attributes for implementing the system are discussed together with suggestions for processing element design. Emphasis is placed on flexible architectures capable of accommodating widely varying application specifics.

Carroll, Chester C.↗
NASA NTRS1988

Development of the network architecture of the Canadian MSAT system

A description is given of the present concept for the Canadian Mobile Satellite (MSAT) System and the development of the network architecture which will accommodate the planned family of three categories of service: a mobile radio service (MRS), a mobile telephone service (MTS), and a mobile data service (MDS). The MSAT satellite will have cross-strapped L-band and Ku-band transponders to provide communications services between L-band mobile terminals and fixed base stations supporting dispatcher-type MRS, gateway stations supporting MTS interconnections to the public telephone network, data hub stations supporting the MDS, and the network control center. The currently perceived centralized architecture with demand assignment multiple access for the circuit switched MRS, MTS and permanently assigned channels for the packet switched MDS is discussed.

Davies, N. George↗
NASA NTRS1987

System architecture for telerobotic servicing and assembly tasks

The architecture of an integrated telerobotics laboratory which is being used for research on the mechanisms, controls, sensing, and operator interface required to accomplish space telerobotic tasks is described. The laboratory hardware is considered, including manipulator and controller, end effector, and vision. The virtual architecture, a common reference model for most of the laboratory applications, is discussed. Teleoperator and robotics system simulations which have been performed using the system are discussed.

Harrison, F. Wallace, Jr.↗