Impact of post metal annealing on gate work function engineering for advanced MOS applications
Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impact of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.