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At least 1,333 records · Page 74

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DOE OSTI2014

Post polymerization cure shape memory polymers

This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

36 MATERIALS SCIENCE↗

DOE OSTI2014

High-Performance Computation of Distributed-Memory Parallel 3D Voronoi and Delaunay Tessellation

Computing a Voronoi or Delaunay tessellation from a set of points is a core part of the analysis of many simulated and measured datasets: N-body simulations, molecular dynamics codes, and LIDAR point clouds are just a few examples. Such computational geometry methods are common in data analysis and visualization; but as the scale of simulations and observations surpasses billions of particles, the existing serial and shared-memory algorithms no longer suffice. A distributed-memory scalable parallel algorithm is the only feasible approach. The primary contribution of this paper is a new parallel Delaunay and Voronoi tessellation algorithm that automatically determines which neighbor points need to be exchanged among the subdomains of a spatial decomposition. Other contributions include periodic and wall boundary conditions, comparison of our method using two popular serial libraries, and application to numerous science datasets.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Case Study in Corporate Memory Recovery: Hanford Tank Farms Miscellaneous Underground Waste Storage Tanks - 15344

In addition to managing the 177 underground waste storage tanks containing 212,000 m3 (56 million gal) of radioactive waste at the U. S. Department of Energy’s Hanford Site 200 Area Tank Farms, Washington River Protection Solutions LLC is responsible for managing numerous small catch tanks and special surveillance facilities. These are collectively known as “MUSTs” - Miscellaneous Underground Storage Tanks. The MUSTs typically collected drainage and flushes during waste transfer system piping changes; special surveillance facilities supported Tank Farm processes including post-World War II uranium recovery and later fission product recovery from tank wastes. Most were removed from service following deactivation of the single-shell tank system in 1980 and stabilized by pumping the remaining liquids from them. The MUSTs were isolated by blanking connecting transfer lines and adding weatherproofing to prevent rainwater entry. Over the next 30 years MUST operating records were dispersed into large electronic databases or transferred to the National Archives Regional Center in Seattle, Washington. During 2014 an effort to reacquire the historical bases for the MUSTs’ published waste volumes was undertaken. Corporate Memory Recovery from a variety of record sources allowed waste volumes to be initially determined for 21 MUSTs, and waste volumes to be adjusted for 37 others. Precursors and symptoms of Corporate Memory Loss were identified in the context of MUST records recovery.

Washenfelder, D. J.↗

DOE OSTI2015

Method for training honeybees to respond to olfactory stimuli and enhancement of memory retention therein

A specialized conditioning protocol for honeybees that is designed for use within a complex agricultural ecosystem. This method ensures that the conditioned bees will be less likely to exhibit a conditioned response to uninfected plants, a false positive response that would render such a biological sensor unreliable for agricultural decision support. Also described is a superboosting training regime that allows training without the aid of expensive equipment and protocols for training in out in the field. Also described is a memory enhancing cocktail that aids in long term memory retention of a vapor signature. This allows the bees to be used in the field for longer durations and with fewer bees trained overall.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2014

A Screen Space GPGPU Surface LIC Algorithm for Distributed Memory Data Parallel Sort Last Rendering Infrastructures

The surface line integral convolution(LIC) visualization technique produces dense visualization of vector fields on arbitrary surfaces. We present a screen space surface LIC algorithm for use in distributed memory data parallel sort last rendering infrastructures. The motivations for our work are to support analysis of datasets that are too large to fit in the main memory of a single computer and compatibility with prevalent parallel scientific visualization tools such as ParaView and VisIt. By working in screen space using OpenGL we can leverage the computational power of GPUs when they are available and run without them when they are not. We address efficiency and performance issues that arise from the transformation of data from physical to screen space by selecting an alternate screen space domain decomposition. We analyze the algorithm's scaling behavior with and without GPUs on two high performance computing systems using data from turbulent plasma simulations.

Loring, Burlen↗

DOE OSTI2016

Mini-Ckpts: Surviving OS Failures in Persistent Memory

Concern is growing in the high-performance computing (HPC) community on the reliability of future extreme-scale systems. Current efforts have focused on application fault-tolerance rather than the operating system (OS), despite the fact that recent studies have suggested that failures in OS memory are more likely. The OS is critical to a system's correct and efficient operation of the node and processes it governs -- and in HPC also for any other nodes a parallelized application runs on and communicates with: Any single node failure generally forces all processes of this application to terminate due to tight communication in HPC. Therefore, the OS itself must be capable of tolerating failures. In this work, we introduce mini-ckpts, a framework which enables application survival despite the occurrence of a fatal OS failure or crash. Mini-ckpts achieves this tolerance by ensuring that the critical data describing a process is preserved in persistent memory prior to the failure. Following the failure, the OS is rejuvenated via a warm reboot and the application continues execution effectively making the failure and restart transparent. The mini-ckpts rejuvenation and recovery process is measured to take between three to six seconds and has a failure-free overhead of between 3-5% for a number of key HPC workloads. In contrast to current fault-tolerance methods, this work ensures that the operating and runtime system can continue in the presence of faults. This is a much finer-grained and dynamic method of fault-tolerance than the current, coarse-grained, application-centric methods. Handling faults at this level has the potential to greatly reduce overheads and enables mitigation of additional fault scenarios.

Fiala, David↗

DOE OSTI2016

Method for programming a flash memory

A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Post polymerization cure shape memory polymers

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2017

Shape-memory polymer foam device for treating aneurysms

A system for treating an aneurysm in a blood vessel or vein, wherein the aneurysm has a dome, an interior, and a neck. The system includes a shape memory polymer foam in the interior of the aneurysm between the dome and the neck. The shape memory polymer foam has pores that include a first multiplicity of pores having a first pore size and a second multiplicity of pores having a second pore size. The second pore size is larger than said first pore size. The first multiplicity of pores are located in the neck of the aneurysm. The second multiplicity of pores are located in the dome of the aneurysm.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2017

Ultra low density biodegradable shape memory polymer foams with tunable physical properties

Compositions and/or structures of degradable shape memory polymers (SMPs) ranging in form from neat/unfoamed to ultra low density materials of down to 0.005 g/cc density. These materials show controllable degradation rate, actuation temperature and breadth of transitions along with high modulus and excellent shape memory behavior. A method of m ly low density foams (up to 0.005 g/cc) via use of combined chemical and physical aking extreme blowing agents, where the physical blowing agents may be a single compound or mixtures of two or more compounds, and other related methods, including of using multiple co-blowing agents of successively higher boiling points in order to achieve a large range of densities for a fixed net chemical composition. Methods of optimization of the physical properties of the foams such as porosity, cell size and distribution, cell openness etc. of these materials, to further expand their uses and improve their performance.

36 MATERIALS SCIENCE↗

DOE OSTI2018

Processor-in-memory-and-storage architecture

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Apparatus and methods for memory using in-plane polarization

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.

42 ENGINEERING↗

DOE OSTI2018

Magnetoelectric memory cells with domain-wall-mediated switching

A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain wall to be trapped within a magnetoelectric antiferromagnetic (MEAF) active layer. An extension of this architecture applies to multiple-gate linear arrays that can offer advantages in memory density, programmability, and logic functionality. Applying a small anisotropic in-plane shear strain to the MEAF can block domain wall precession to improve reliability and speed of switching.

42 ENGINEERING↗

DOE OSTI2015

Ground-referenced single-ended memory interconnect

A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Dally, William J.↗

DOE OSTI2014

Optimizing TLB entries for mixed page size storage in contiguous memory

A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Chen, Dong↗

DOE OSTI2019

Memory node controller

A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

DOE OSTI2019

Shape memory embolectomy devices and systems

An embolectomy device comprised of an expansion unit and a support unit is disclosed. The expansion unit can be actuated in response to one or more external stimuli, and the support unit, located proximately to the expansion unit, provides a force to hold the expansion unit in place and to further induce the expansion unit's radial expansion. The radial expansion of the expansion unit causes the expansion unit to physically contact a blood clot, enabling the blood clot to be removed. In some embodiments, the expansion unit can be fabricated from a shape memory polymer foam. In some embodiments the support unit can be fabricated from any elastic material including, without limitation, shape memory alloys.

Szafron, Jason↗

DOE OSTI2021

A Memory Efficient Lock-Free Circular Queue

Hardware queues are import in many applications, such as data transfer, synchronization of concurrent modules with the need of mutual exclusion constructs. State of the art bounded (of a fixed size) lock free circular queues are implemented either by read/write atomic operations, or barrier conditions, or by separating dequeue and enqueue operations. However, these queues always require an unused element at all the times to safe-guard the front and rear pointers of the queue, so as to avoid data race conditions, which leads to the waste of memory. The waste of memory is especially disadvantageous in applications such as I/O data transfer, and image transfer between processing filters, when large element size is needed, We propose a lock-free solution of the bounded circular queue through read/write atomic operations, but without the need of an extra element in the queue. The proposed solution is implemented and verified in both Verilog and ’C’ languages. We also demonstrate its effectiveness by comparing its area and delay metrics with the implementations of other existing designs of queue.

Miniskar, Narasinga Rao↗