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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,333 records · Page 74
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗
DOE OSTI2017

Diagnostics, Control and Performance Parameters for the BELLA High Repetition Rate Petawatt Class Laser

A laser system producing controllable and stable pulses with high power and ultrashort duration at high repetition rate is a key component of a high energy laser-plasma accelerator (LPA). Precise characterization and control of laser properties are essential to understanding laser-plasma interactions required to build a 10-GeV class LPA. This study discusses the diagnostics, control and performance parameters of a 1 Hz, 1 petawatt (PW) class laser at the Berkeley Lab Laser Accelerator (BELLA) facility. The BELLA PW laser provided up to 46 J on target with a 1% level energy fluctuation and 1.3-μrad pointing stability. The spatial profile was measured and optimized by using a camera, wavefront sensor, and deformable mirror (ILAO system). The focus waist was measured to be r 0 = 53 μm and the fraction of energy within the circular area defined by the first minimum of the diffraction pattern (r = 67 μm) was 0.75. The temporal profile was controlled via the angle of incidence on a stretcher and a compressor, as well as an acousto-optic programmable dispersive. The temporal pulse shape was measured to be about 33 fs in full width at half maximum (WIZZLER and GRENOUILLE diagnostics). In order to accurately evaluate peak intensity, the energy-normalized peak fluence, and energy-normalized peak power were analyzed for the measured spatial and temporal mode profiles, and were found to be 15 kJ/(cm 2 J) with 6% fluctuation (standard deviation) and 25 TW/J with 5% fluctuation for 46-J on-target energy, respectively. This yielded a peak power of 1.2 PW and a peak intensity of 17×10 18 W/cm 2 with 8% fluctuation. A method to model the pulse shape for arbitrary compressor grating distance with high accuracy was developed. The pulse contrast above the amplified spontaneous emission pedestal was measured by SEQUOIA and found to be better than 10 9 . The first order spatiotemporal couplings (STCs) were measured with GRENOUILLE, and a simulation of the pulse's evolution at the vicinity of the target was presented. A maximum pulse front tilt angle of less than 7 mrad was achieved. The reduction of the peak power caused by the first order STCs was estimated to be less than 1%. Finally, the capabilities described in this paper are essential for generation of high quality electron beams.

47 OTHER INSTRUMENTATION↗
DOE OSTI2017

FPGA-Based Optical Cavity Phase Stabilization for Coherent Pulse Stacking

Coherent pulse stacking (CPS) is a new time-domain coherent addition technique that stacks several optical pulses into a single output pulse, enabling high pulse energy from fiber lasers. We develop a robust, scalable, and distributed digital control system with firmware and software integration for algorithms, to support the CPS application. We model CPS as a digital filter in the Z domain and implement a pulse-pattern-based cavity phase detection algorithm on an field-programmable gate array (FPGA). A two-stage (2+1 cavities) 15-pulse stacking system achieves an 11.0 peak-power enhancement factor. Each optical cavity is fed back at 1.5kHz, and stabilized at an individually-prescribed round-trip phase with 0.7deg and 2.1deg rms phase errors for Stages 1 and 2, respectively. Optical cavity phase control with nanometer accuracy ensures 1.2% intensity stability of the stacked pulse over 12 h. The FPGA-based feedback control system can be scaled to large numbers of optical cavities.

43 PARTICLE ACCELERATORS↗
DOE OSTI2017

Noise Radar Approach for Interrogating SAW Sensors Using Software Defined Radio

Passive, wireless surface acoustic wave (SAW) sensor systems can be approached from a radar perspective, where the SAW device is thought of as a cooperative target. Here, this paper investigates the use of a commercial-off-the-shelf software defined radio to interrogate wireless SAW sensors with a randomly generated interrogation pulse. The USRP B200mini is utilized as the transceiver platform with custom field-programmable gate array (FPGA) modifications to generate the random interrogation waveform and provide synchronization and buffering to the received signal. Each transmit sample bit in the FPGA is fed by an independent linear-feedback shift register, which generates pseudo-random I and Q samples for the interrogation pulse. An RF daughterboard has also been developed and integrated with the B200mini to increase the transmit power, provide filtering of the RF signals, and switch a signal antenna between the transmit and receive channels. Radio control and matched filter correlator post-processing are accomplished using Python. Design and implementation details for the FPGA modifications, RF daughterboard, and post-processing are discussed. Lastly, the system is demonstrated by wirelessly interrogating SAW temperature sensors at 915 MHz.

47 OTHER INSTRUMENTATION↗
DOE OSTI2017

Network Hardware Virtualization for Application Provisioning in Core Networks

We present that service providers and vendors are moving toward a network virtualized core, whereby multiple applications would be treated on their own merit in programmable hardware. Such a network would have the advantage of being customized for user requirements and allow provisioning of next generation services that are built specifically to meet user needs. In this article, we articulate the impact of network virtualization on networks that provide customized services and how a provider's business can grow with network virtualization. We outline a decision map that allows mapping of applications with technology that is supported in network-virtualization - oriented equipment. Analogies to the world of virtual machines and generic virtualization show that hardware supporting network virtualization will facilitate new customer needs while optimizing the provider network from the cost and performance perspectives. A key conclusion of the article is that growth would yield sizable revenue when providers plan ahead in terms of supporting network-virtualization-oriented technology in their networks. To be precise, providers have to incorporate into their growth plans network elements capable of new service deployments while protecting network neutrality. Finally, a simulation study validates our NV-induced model.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

PyOMP: Multithreaded Parallel Programming in Python

We know that Python is a widely used language in scientific computing. When the goal is high performance, however, Python lags far behind low-level languages such as C and Fortran. To support applications that stress performance, Python needs to access the full capabilities of modern CPUs. That means support for parallel multithreading. In this paper, we describe PyOMP, a system that enables OpenMP in Python. Programmers write code in Python with OpenMP, Numba generates code that compiles to LLVM, and the resulting programs run with performance that approaches that from code written with C and OpenMP. In this paper we provide an update on the PyOMP project and explain how to install it and use it to write parallel multithreaded code in Python.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Optimized Quantum Compilation for Near-Term Algorithms with OpenPulse

Quantum computers are traditionally operated by programmers at the granularity of a gate-based instruction set. However, the actual device-level control of a quantum computer is performed via analog pulses. Here, we introduce a compiler that exploits direct control at this microarchitectural level to achieve significant improvements for quantum programs. Unlike quantum optimal control, our approach is bootstrapped from existing gate calibrations and the resulting pulses are simple. Our techniques are applicable to any quantum computer and realizable on current devices. We validate our techniques with millions of experimental shots on IBM quantum computers, controlled via the OpenPulse control interface. For representative benchmarks, our pulse control techniques achieve both 1.6x lower error rates and 2x faster execution time, relative to standard gate-based compilation. These improvements are critical in the near-term era of quantum computing, which is bottlenecked by error rates and qubit lifetimes.

Gokhale, Pranav↗
DOE OSTI2022

Retargetable Optimizing Compilers for Quantum Accelerators via a Multi-Level Intermediate Representation

In this work, we present a multi-level quantum-classical intermediate representation (IR) that enables an optimizing, retargetable compiler for available quantum languages. Our work builds upon the Multi-level Intermediate Representation (MLIR) framework and leverages its unique progressive lowering capabilities to map quantum languages to the LLVM machine-level IR. We provide both quantum and classical optimizations via the MLIR pattern rewriting sub-system and standard LLVM optimization passes, and demonstrate the programmability, compilation, and execution of our approach via standard benchmarks and test cases. In comparison to other standalone language and compiler efforts available today, our work results in compile times that are 1000x faster than standard Pythonic approaches, and 5-10x faster than comparative standalone quantum language compilers. Our compiler provides quantum resource optimizations via standard programming patterns that result in a 10x reduction in entangling operations, a common source of program noise. We see this work as a vehicle for rapid quantum compiler prototyping.

43 PARTICLE ACCELERATORS↗
DOE OSTI2016

Development of a 6LiF/ZnS-based Neutron Multiplicity Counter

Abstract–Neutron multiplicity counters are used in safeguards to provide rapid assay of samples which contain an unknown amount of plutonium in a potentially unknown configuration. A project at PNNL is using regular and nickel-quenched 6LiF/ZnS neutron-scintillator sheets and wavelength shifting plastic for light pipes in place of 3He. A combination of laboratory and modeling work predicts a LiF/ZnS-based system to be able to match or exceed the performance of the best 3He-based systems available. Also, the Ni-quenched material is expected to allow for improved neutron/gamma-ray discrimination at twice the event rate relative to the non-Ni-quenched LiF/ZnS. A new system based on the LiF/ZnS material is under construction and components are being used to optimize the detection efficiency and neutron/gamma-ray discrimination properties. Components of the new system are partially constructed and undergoing performance testing utilizing high-speed digitizers with field programmable gate arrays to perform the neutron/gamma-ray discrimination. The expected performance of the full-scale system is expected to be nearly the same as for 3He-based systems and is due for completion in 2016.

Stave, Sean C.↗
DOE OSTI2016

Development of flexible, scalable, low cost readout for beam tests of the high granularity calorimeter for the CMS endcap

As part of the development of the High Granularity Calorimeter for the CMS Endcap at HL-LHC, The CMS collaboration is conducting a comprehensive series of beam tests. The first beam test, with a single HGC module was carried out in March of 2016 at the Fermilab Test Beam Facility, continuing to a 16 module test in July of 2016. We describe here the development of a low cost readout system that is simple to implement and is able to grow with the system under test. The system is based on the low cost Zynq SoC that allows simple DAQ development in a Linux environment. For this application we used the Digilent ZedBoard, which allows high speed LVDS links and Linux software development on a single commercial board. A small custom FPGA board designed to comply with the VITA 57 Field Programmable Mezzanine Card standard implements the interface to the readout ASIC mounted on the HGC sensor modules and provides the LVDS links to the ZedBoard, either directly over the FMC connector or via a custom carrier card. This architecture provides scalability, ease of development and low cost.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Case Study of Using Kokkos and SYCLs Performance-Portable Frameworks for Milc-Dslash Benchmark on NVIDIA, AMD and Intel GPUs

Six of the top ten supercomputers in the TOP500 list from June 2021 rely on NVIDIA GPUs to achieve their peak compute bandwidth. With the announcement of Aurora, Frontier, and El Capitan, Intel and AMD have also entered the domain of providing GPUs for scientific computing. A consequence of the increased diversity in the GPU landscape is the emergence of portable programming models such as Kokkos, SYCL, OpenCL, and OpenMP, which allow application developers to maintain a single-source code across a diverse range of hardware architectures. While the portable frameworks try to optimize the compute resource usage on a given architecture, it is the programmers responsibility to expose parallelism in an application that can take advantage of thousands of processing elements available on GPUs. In this paper, we introduce a GPU-friendly parallel implementation of Milc-Dslash that exposes multiple hierarchies of parallelism in the algorithm. Milc-Dslash was designed to serve as a benchmark with highly optimized matrix-vector multiplications to measure the resource utilization on the GPU systems. The parallel hierarchies in the Milc-Dslash algorithm are mapped onto a target hardware using Kokkos and SYCL programming models. We present the performance achieved by Kokkos and SYCL implementations of Milc-Dslash on NVIDIA A100 GPU, AMD MI100 GPU, and Intel Gen9 GPU. Additionally, we compare the Kokkos and SYCL performances with those obtained from the versions written in CUDA and HIP programming models on NVIDIA A100 GPU and AMD MI100 GPU, respectively.

Dufek, Amanda S↗
DOE OSTI2018

Comparison of Doubly-Fed Induction Generator Machine Models for Real-Time Simulations

This work presents a detailed comparison among three implementations of the Doubly-Fed Induction Generator (DFIG) machine model. The alpha-beta-gamma, synchronous (dqo), and natural frame dynamic machine models were deployed on a Field-Programmable Gate Array (FPGA) and compared in terms of execution time and resource utilization. These machine models were also validated against a physical DFIG machine during balanced and unbalanced grid conditions. A benchmark is presented with the objective of selecting the machine model, orientation and state-space representation that is best suited for real-time simulations. The selected machine model is used to develop a real-time emulator of a Type-3 wind system. This emulator enables the study of wind turbine system in realtime using a validated platform while allowing controller testing without relying on expensive third-party solutions.

Ferrari Maglia, Max↗
DOE OSTI2025

A High-Current Pulsed Prototype Power Supply

The Accelerator Controls Operations Research Network (ACORN) project aims to modernize the accelerator control system and replace aging power supplies at Fermilab. As part of this effort, outdated RF ferrite bias power supplies will be redesigned. These power supplies are essential for tuning the resonant frequency of RF cavities by delivering programmable current outputs of up to 2500 A and voltages ranging from −10 V to +35 V. They operate at a repetition rate of 15 Hz in the Booster ring, and 1 Hz at the Main Injector ring. The power supplies utilize a bank of transistors in the linear region, connected in parallel with the load, to actively regulate the output current from a 12-pulse SCR bridge. To support this upgrade, a new bias power supply topology was developed as proof of concept. The design utilizes an IGBT Hbridge operating in Pulse Width Modulation (PWM) mode, controlled by a microcontroller. A prototype, constructed using spare components, successfully delivered an output current of 500 A at a repetition rate of 15 Hz during initial testing. The circuit's bandwidth was measured at 480 Hz, highlighting opportunities for further optimization in the controller design to achieve the target bandwidth of 2 kHz.

Bullman, Austin [ORNL]↗
DOE OSTI2020

IEEE 1547-2018 Based Interoperable PV Inverter with Advanced Grid-Support Functions

Grid integration of photovoltaic (PV) inverters has been increasing in the past decade. As a result of the uncertainties introduced with high penetrations of PV, better monitoring and control of the PV inverters becomes crucial for improving overall system stability. This paper focuses on the communications capability of the inverter controller and on enabling interoperability. Multiple standards are available to enable interoperability in PV inverters. In this paper, an interoperable controller, enabled by Distributed Network Protocol 3 (DNP3) communications protocols, is developed for a grid-connected, three-phase PV inverter. The DNP3 server for the PV inverter is programmed on the real-time layer of the field-programmable gate array (FPGA)-based inverter controller. Set points for advanced inverter control functions, such as volt/VAr curves, ride-through curves, are sent from a DNP3 client, a simulated distribution management system application, to the PV inverter through DNP3. This communications capability of the inverter controller is validated using a controller-hardware-in-the-loop experimental setup. The code developed to achieve the interoperability is available in the public domain through open-source software licensing. This interoperability will enable smoother grid integration of smart PV inverters with advanced grid-support functions as well as allow better monitoring and control of PV inverters for grid stability.

14 SOLAR ENERGY↗
DOE OSTI2021

Consensus International Solar Resource Standards and Best Practices Development

Standardization and best practices of data sets and models enable the industry to develop widely accepted protocols adapted to various stages of solar project development and operations. In collaboration with the International Energy Agency Photovoltaic Power Systems Programme Task 16, the National Renewable Energy Laboratory (NREL) developed and regularly updates the Best Practices Handbook for the Collection and Use of Solar Resource Data for Solar Energy Applications. In collaboration with ASTM's radiometry subcommittee, NREL leads the development of various radiometric standards. These contribute to increased accuracy in the measurement of the solar resource available to conversion systems and boost the development and improvement of radiative models. These models can then provide the long-term geographic or climatic distribution of solar radiation for areas where measured solar data are not available. Further, these standards play a preeminent role in all aspects of solar energy projects, including standard conditions, methods and instrumentation, accelerated testing, and service lifetime of materials.

ASTM↗
DOE OSTI2020

Extending XACC for Quantum Optimal Control

Quantum computing vendors are beginning to open up application programming interfaces for direct pulse-level quantum control. With this, programmers can begin to describe quantum kernels of execution via sequences of arbitrary pulse shapes. This opens new avenues of research and development with regards to smart quantum compilation routines that enable direct translation of higher-level digital assembly representations to these native pulse instructions. In this work, we present an extension to the XACC system-level quantum-classical software framework that directly enables this compilation lowering phase via user-specified quantum optimal control techniques. This extension enables the translation of digital quantum circuit representations to equivalent pulse sequences that are optimal with respect to the backend system dynamics. Our work is modular and extensible, enabling third party optimal control techniques and strategies in both C++ and Python. We demonstrate this extension with familiar gradient-based methods like gradient ascent pulse engineering (GRAPE), gradient optimization of analytic controls (GOAT), and Krotov's method. Our work serves as a foundational component of future quantum-classical compiler designs that lower high-level programmatic representations to low-level machine instructions.

Nguyen, Thien↗
DOE OSTI2014

Structure Slicing: Extending Logical Regions with Fields, In: SC '14: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

Applications on modern supercomputers are increasingly limited by the cost of data movement, but mainstream programming systems have few abstractions for describing the structure of a program's data. Consequently, the burden of managing data movement, placement, and layout currently falls primarily upon the programmer. To address this problem we previously proposed a data model based on logical regions and described Legion, a programming system incorporating logical regions. In this paper, we present structure slicing, which incorporates fields into the logical region data model. We show that structure slicing enables Legion to automatically infer task parallelism from field non-interference, decouple the specification of data usage from layout, and reduce the overall amount of data moved. We demonstrate that structure slicing enables both strong and weak scaling of three Legion applications including S3D, a production combustion simulation that uses logical regions with thousands of fields, with speedups of up to 3.68X over a vectorized CPU-only Fortran implementation and 1.88X over an independently hand-tuned OpenACC code.

Computer Science↗
DOE OSTI2024

AutoCheck: Automatically Identifying Variables for Checkpointing by Data Dependency Analysis

Checkpoint/Restart (C/R) has been widely deployed in numerous HPC systems, Clouds, and industrial data centers, which are typically operated by system engineers. Nevertheless, there is no existing approach that helps system engineers without domain expertise and domain scientists without system fault tolerance knowledge identify those critical variables accounted for correct application execution restoration in a failure for C/R. To address this problem, we propose an analytical model and a tool (AutoCheck) that can automatically identify critical variables to checkpoint for C/R. AutoCheck relies on first, analytically tracking and optimizing data dependency between variables and other application execution state, and second, a set of heuristics that identify critical variables for checkpointing from the refined data dependency graph (DDG). AutoCheck allows programmers to pinpoint critical variables to checkpoint quickly within a few minutes. We evaluate AutoCheck on 13 representative HPC benchmarks, demonstrating that AutoCheck can efficiently identify correct critical variables to checkpoint.

HPC↗