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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,333 records · Page 74
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Particle-sampling statistics in laser anemometers Sample-and-hold systems and saturable systems

The effect of the data-processing system on the particle statistics obtained with laser anemometry of flows containing suspended particles is examined. Attention is given to the sample and hold processor, a pseudo-analog device which retains the last measurement until a new measurement is made, followed by time-averaging of the data. The second system considered features a dead time, i.e., a saturable system with a significant reset time with storage in a data buffer. It is noted that the saturable system operates independent of the particle arrival rate. The probabilities of a particle arrival in a given time period are calculated for both processing systems. It is shown that the system outputs are dependent on the mean particle flow rate, the flow correlation time, and the flow statistics, indicating that the particle density affects both systems. The results are significant for instances of good correlation between the particle density and velocity, such as occurs near the edge of a jet.

Edwards, R. V.↗
DOE OSTI2013

End-System Network Interface Controller for 100 Gb/s Wide Area Networks: Final Report

In recent years, network bandwidth requirements have scaled multiple folds, pushing the need for the development of data exchange mechanisms at 100 Gb/s and beyond. High performance computing, climate modeling, large-scale storage, and collaborative scientific research are examples of applications that can greatly benefit by leveraging high bandwidth capabilities of the order of 100 Gb/s. Such requirements and advances in IEEE Ethernet standards, Optical Transport Unit4 (OTU4), and host-system interconnects demand a network infrastructure supporting throughput rates of the order of 100 Gb/s with a single wavelength. To address such a demand Acadia Optronics in collaboration with the University of New Mexico, proposed and developed a end-system Network Interface Controller (NIC) for the 100Gbps WANs. Acadia’s 100G NIC employs an FPGA based system with a high-performance processor interconnect (PCIe 3.0) and a high capacity optical transmission link (CXP) to provide data transmission at the rate of 100 Gbps.

100 Gb/s network interface controller↗
NASA NTRS2011

Mission Planning and Sequencing Investigation of Third Party Software

Mission Planning and Sequencing (MPS) maintains a system called the Automated Sequence Processor(ASP) which is responsible for checking non?interactive commands and preparing them for radiation to spacecraft. In order to streamline the process and increase maintainability MPS is looking to use a third party workflow engine to control the ASP. In addition to increasing productivity, another driver for the workflow paradigm is the new way that the software is going to represent the spacecraft state. The spacecraft state is going to be represented by a timeline data structure.

work flow engine↗
NASA NTRS1979

A comparison of WFTA and FFT programs

Bounds on the minimum number of data transfers (i.e., loads and stores) required by WFTA (Winograd Fourier Transform Algorithm) and FFT programs are presented. The analysis is applicable to those general-purpose computers with a small number of general processor registers (e.g., the IBM370, PDP-11, etc.). It is shown that the 1008-point WFTA requires about 21% more data transfers than the 1024-point radix-4 FFT; on the other hand, the 120-point WFTA has about 22% fewer data transfers than the 128-point radix-2 FFT. Finally, comparisons of the 'total' program execution times (multiplications, additions, and data transfers, but not indexing or permutations) are presented.

Nawab, H.↗
NASA NTRS1983

Three-dimensional flow over a conical afterbody containing a centered propulsive jet - A numerical simulation

The supersonic flow field over a body of revolution incident to the free stream is simulated numerically on a large, array processor (the CDC Cyber 205). The configuration is composed of a cone-cylinder forebody followed by a conical afterbody from which emanates a centered, supersonic propulsive jet. The free-stream Mach number is 2, the jet-exit Mach number is 2.5, and the jet-to-free-stream static pressure ratio is 3. Both the external flow and the exhaust are ideal air at a common total temperature. The thin-layer approximation to the time-dependent, compressible, Reynolds-averaged Navier-Stokes equations are solved using an implicit finite-difference algorithm. The data base, of 5 million words, is structured in a 'pencil' format so that efficient use of the array processor can be realized. The computer code is completely vectorized to take advantage of the data structure. Turbulence closure is achieved using an empirical algebraic eddy-viscosity model. The configuration and flow conditions correspond to published experimental tests and the computed solutions are consistent with the experimental data.

Deiwert, G. S.↗
NASA NTRS1980

Concerning the feasibility of a real time SAR digital processor for VOIR low resolution imaging modes

The feasibility of real time digital processing of synthetic aperture radar data for Venus orbiting imaging radar low resolution modes was investigated. First, it is shown that range migration is not a problem for these modes. Then, under the assumption of no range migration, fast Fourier transform implementations for accomplishing both range and azimuth correlation in real time are shown to be feasible with current technology.

Truong, T. K.↗
NASA NTRS1980

Considerations on real-time processing of spaceborne synthetic aperture radar data

This paper comprises a description of Synthetic Aperture Radar (SAR) processing approaches and a discussion on the processor complexity measures. The objective of the paper is to provide basic system knowledge on the design of a real-time signal processor for spaceborne synthetic aperture radar. A review of SAR sensor performance capability and general electronic processing approaches will be given first. The discussion of SAR processor complexity is divided into two areas: the arithmetic complexity and the control complexity. A generalized treatment of these subjects is provided. The results could be readily extended to special cases.

Wu, C.↗
NASA NTRS1988

Definition of an auxiliary processor dedicated to real-time operating system kernels

In order to increase the efficiency of process control data processing, it is necessary to enhance the productivity of real time high level languages and to automate the task administration, because presently 60 percent or more of the applications are still programmed in assembly languages. This may be achieved by migrating apt functions for the support of process control oriented languages into the hardware, i.e., by new architectures. Whereas numerous high level languages have already been defined or realized, there are no investigations yet on hardware assisted implementation of real time features. The requirements to be fulfilled by languages and operating systems in hard real time environment are summarized. A comparison of the most prominent languages, viz. Ada, HAL/S, LTR, Pearl, as well as the real time extensions of FORTRAN and PL/1, reveals how existing languages meet these demands and which features still need to be incorporated to enable the development of reliable software with predictable program behavior, thus making it possible to carry out a technical safety approval. Accordingly, Pearl proved to be the closest match to the mentioned requirements.

Halang, Wolfgang A.↗
NASA NTRS2021

NASA SpaceCube Edge TPU SmallSat Card for Autonomous Operations and Onboard Science-Data Analysis

Using state-of-the-art artificial intelligence (AI)frameworks onboard spacecraft is challenging because common spacecraft processors cannot provide comparable performance to datacenters with server-grade CPUs and GPUs available for terrestrial applications and advanced deep-learning networks. This limitation makes small, lo w-p o we r AI microchip architectures, such as the Google Coral Edge Tensor Processing Unit (TPU), attractive for space missions where the application-specific design enables both high-performance and power-efficient computing for AI applications. To address these challenging considerations for space deployment, this research introduces the design and capabilities of a CubeSat-sized Edge TPU-based co-processor card, known as the SpaceCube Low-power Ed g e Artificial Intelligence Resilient Node (SC-LEARN). This design conforms to NASA’s CubeSat Card Specification (CS2) for integration into next-generation SmallSat and CubeSat systems. This paper describes the overarching architecture and design of the SC-LEARN, as well as, the supporting test card designed for rapid prototyping and evaluation. The SC-LEARN was developed with three operational modes: (1) a high-performance parallel-processing mode,(2)a fault-tolerant mode for onboard resilience, and (3) a power-saving mode with cold spares. Importantly, this research also elaborates on both training and quantization of Tensor Flow models for the SC-LEARN for use onboard with representative, open-source datasets. Lastly, we describe future research plans, including radiation-beam testing and flight demonstration.

Advanced avionics↗
DOE OSTI2014

Evaluation of Low Power ARM Processors for Monte Carlo Particle Transport: MCNP6 on the ARM Cortex-A8 - Paper 83

In the push towards exascale computing, the limiting factors are power requirements and heat dissipation. Using current technology, the power required to drive an exascale supercomputer would near 400-MW. Clearly, future computing hardware will have to be more energy efficient in order to achieve exascale performance. Most of the current research in advanced computing architectures is in the use of standard CPUs with accelerators. However, these accelerators are not generally supported by the traditional scientific programming languages (C, C++, and Fortran) and the scientific software must be tailored specifically to take advantage of the accelerators. Large scale scientific software (hundreds-of-thousand to millions of lines of code) can not be easily ported to the computing platform du jour. The widespread use of low power ARM based processors in the mobile computing market offer a low power alternative to accelerators that are also supported by the traditional scientific programming languages and programming paradigms such as MPI and OpenMP. Computing architectures for scientific computing are often assessed using standard benchmarks such as LINPACK benchmark or using suites of mini-applications that are greatly simplified stand-ins for scientific software. Often the real applications that will deployed on the scientific supercomputers are not ported or tested until delivery of the machines. In order to evaluate the use of ARM processors for scientific computing the Monte Carlo particle transport code, MCNP version 6 was compiled on the ARM Cortex-A8 and a set of benchmark problems were used to assess performance in comparison to an Intel Xeon E5-2670 and the low power Intel Atom N270. MCNP is a continuous energy Monte Carlo particle transport code in development at Los Alamos National Laboratory since 1977. MCNP is used to transport neutrons, photon, electrons, and charged particles using continuous energy interaction data. It is commonly used in fields of nuclear power, nuclear medicine, radiation protection, and high-energy physics through-out the world. MCNP version 6 is approximately 450 thousand lines of code, written primary in Fortran90, with some C and C++. MCNP supports distributed multiprocessing using MPI and threading with OpenMP. The ARM Cortex-A8 executes MCNP6 using about twice as much power as the Intel Xeon E5-2670 and about the same amount of power as the Intel Atom N270. However, these results are encouraging for the use of low-power ARM chips in future supercomputers. The ARM Cortex-A8 is a 32-bit CPU and it's NEON general-purpose SIMD (single-instruction multiple data) engine does not support double-precision floating-point arithmetic. More recent ARM processors (ARM Cortex-A53 and Cortex-A57) support 64-bit addressing and have NEON co-processors that support double-precision floating-point arithmetic. ARM claims that the A50 series delivers a performance increase of 15 times the Cortex-A8 performance for similar power usage. (authors)

61 RADIATION PROTECTION AND DOSIMETRY↗
DOE OSTI2018

Image Matrix Processor for Volumetric Computations Final Report CRADA No. TSB-1148-95

The development of an Image Matrix Processor (IMP) was proposed that would provide an economical means to perform rapid ray-tracing processes on volume "Giga Voxel" data sets. This was a multi-phased project. The objective of the first phase of the IMP project was to evaluate the practicality of implementing a workstation-based Image Matrix Processor for use in volumetric reconstruction and rendering using hardware simulation techniques. Additionally, ARACOR and LLNL worked together to identify and pursue further funding sources to complete a second phase of this project.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2019

NEXT Single String Integration Tests in Support of the Double Asteroid Redirection Test Mission

A system integration test has been performed utilizing a prototype model NEXT ion thruster, an engineering model power processing unit, and a laboratory model command and data handling system. The objectives of the test were to: a) verify that the integrated system meets performance requirements, b) demonstrate that the integrated system is functional across the anticipated thermal, power processor, and Xe propellant ranges for the DART mission, and to c) evaluate fault detection and operation of the command and data handling system. Measurements made during this test included: thruster performance, PPU input voltages, PPU electrical and thermal telemetry, software states, and fault flags. Additionally, a far-field electrostatic probe diagnostic was used to infer relative changes in the thrust vector across the various propellant flow splits. This manuscript presents the results of these tests, which include integrated ion propulsion system demonstrations of performance, details on the execution of DART flight algorithms, and software fault handling.

Thomas, Robert E.↗
NASA NTRS2019

NEXT Single String Integration Tests in Support of the Double Asteroid Redirection Test Mission

A system integration test has been performed utilizing a prototype model NEXT ion thruster, an engineering model power processing unit, and a laboratory model command and data handling system. The objectives of the test were to: a) verify that the integrated system meets performance requirements, b) demonstrate that the integrated system is functional across the anticipated thermal, power processor, and Xe propellant ranges for the DART mission, and to c) evaluate fault detection and operation of the command and data handling system. Measurements made during this test included: thruster performance, PPU input voltages, PPU electrical and thermal telemetry, software states, and fault flags. Additionally, a far-field electrostatic probe diagnostic was used to infer relative changes in the thrust vector across the various propellant flow splits. This manuscript presents the results of these tests, which include integrated ion propulsion system demonstrations of performance, details on the execution of DART flight algorithms, and software fault handling.

Thomas, Robert↗
NASA NTRS1987

A computer controlled signal preprocessor for laser fringe anemometer applications

The operation of most commercially available laser fringe anemometer (LFA) counter-processors assumes that adjustments are made to the signal processing independent of the computer used for reducing the data acquired. Not only does the researcher desire a record of these parameters attached to the data acquired, but changes in flow conditions generally require that these settings be changed to improve data quality. Because of this limitation, on-line modification of the data acquisition parameters can be difficult and time consuming. A computer-controlled signal preprocessor has been developed which makes possible this optimization of the photomultiplier signal as a normal part of the data acquisition process. It allows computer control of the filter selection, signal gain, and photo-multiplier voltage. The raw signal from the photomultiplier tube is input to the preprocessor which, under the control of a digital computer, filters the signal and amplifies it to an acceptable level. The counter-processor used at Lewis Research Center generates the particle interarrival times, as well as the time-of-flight of the particle through the probe volume. The signal preprocessor allows computer control of the acquisition of these data.Through the preprocessor, the computer also can control the hand shaking signals for the interface between itself and the counter-processor. Finally, the signal preprocessor splits the pedestal from the signal before filtering, and monitors the photo-multiplier dc current, sends a signal proportional to this current to the computer through an analog to digital converter, and provides an alarm if the current exceeds a predefined maximum. Complete drawings and explanations are provided in the text as well as a sample interface program for use with the data acquisition software.

Oberle, Lawrence G.↗
NASA NTRS2011

IONAC-Lite

The Interplanetary Overlay Net - working Protocol Accelerator (IONAC) described previously in The Inter - planetary Overlay Networking Protocol Accelerator (NPO-45584), NASA Tech Briefs, Vol. 32, No. 10, (October 2008) p. 106 (http://www.techbriefs.com/component/ content/article/3317) provides functions that implement the Delay Tolerant Networking (DTN) bundle protocol. New missions that require high-speed downlink-only use of DTN can now be accommodated by the unidirectional IONAC-Lite to support high data rate downlink mission applications. Due to constrained energy resources, a conventional software implementation of the DTN protocol can provide only limited throughput for any given reasonable energy consumption rate. The IONAC-Lite DTN Protocol Accelerator is able to reduce this energy consumption by an order of magnitude and increase the throughput capability by two orders of magnitude. In addition, a conventional DTN implementation requires a bundle database with a considerable storage requirement. In very high downlink datarate missions such as near-Earth radar science missions, the storage space utilization needs to be maximized for science data and minimized for communications protocol-related storage needs. The IONAC-Lite DTN Protocol Accelerator is implemented in a reconfigurable hardware device to accomplish exactly what s needed for high-throughput DTN downlink-only scenarios. The following are salient features of the IONAC-Lite implementation: An implementation of the Bundle Protocol for an environment that requires a very high rate bundle egress data rate. The C&DH (command and data handling) subsystem is also expected to be very constrained so the interaction with the C&DH processor and the temporary storage are minimized. Fully pipelined design so that bundle processing database is not required. Implements a lookup table-based approach to eliminate multi-pass processing requirement imposed by the Bundle Protocol header s length field structure and the SDNV (self-delimiting numeric value) data field formatting. 8-bit parallel datapath to support high data-rate missions. Reduced resource utilization implementation for missions that do not require custody transfer features. There was no known implementation of the DTN protocol in a field programmable gate array (FPGA) device prior to the current implementation. The combination of energy and performance optimization that embodies this design makes the work novel.

Torgerson, Jordan L.↗
DOE OSTI2016

Global‐view coefficients: a data management solution for parallel quantum Monte Carlo applications

Summary Quantum Monte Carlo (QMC) applications perform simulation with respect to an initial state of the quantum mechanical system, which is often captured by using a cubic B‐spline basis. This representation is stored as a read‐only table of coefficients and accesses to the table are generated at random as part of the Monte Carlo simulation. Current QMC applications, such as QWalk and QMCPACK, replicate this table at every process or node, which limits scalability because increasing the number of processors does not enable larger systems to be run. We present a partitioned global address space approach to transparently managing this data using Global Arrays in a manner that allows the memory of multiple nodes to be aggregated. We develop an automated data management system that significantly reduces communication overheads, enabling new capabilities for QMC codes. Experimental results with QWalk and QMCPACK demonstrate the effectiveness of the data management system. Copyright © 2016 John Wiley & Sons, Ltd.

Niu, Qingpeng↗
NASA NTRS1978

LANDSAT-2 and LANDSAT-3 Flight evaluation report

Flight performance analysis of LANDSAT 2 and LANDSAT 3 are presented for the period July 1978 to October 1978. Spacecraft operations and orbital parameters are summarized for each spacecraft. Data are provided on the performance and operation of the following subsystems onboard the spacecraft: power; attitude control; command/clock; telemetry; orbit adjust; magnetic moment compensating assembly; unified S band/premodulation processor; electrical interface; thermal narrowband tape recorders; wideband telemetry; attitude measurement sensor; wideband video tape recorders; return beam vidicon; multispectral scanner subsystem; and data collections.

Winchester, T. W.↗