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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Sodium silicate prevents spattered silicon from fusing with surrounding material. Sodium silicate solution applied to wafer by dipping and draining or by spinning; application by spraying also works. When dried in oven, solution leaves thin coating of sodium silicate glass.
Fixtures and techniques are undergoing development. Four test fixtures and two advanced techniques developed in continuing efforts to improve RF characterization of MMIC's. Finline/waveguide test fixture developed to test submodules of 30-GHz monolithic receiver. Universal commercially-manufactured coaxial test fixture modified to enable characterization of various microwave solid-state devices in frequency range of 26.5 to 40 GHz. Probe/waveguide fixture is compact, simple, and designed for non destructive testing of large number of MMIC's. Nondestructive-testing fixture includes cosine-tapered ridge, to match impedance wavequide to microstrip. Advanced technique is microwave-wafer probing. Second advanced technique is electro-optical sampling.
In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.
Although solar cells usually have chips and cracks, no material specifications concerning the allowable crack size on solar cells are available for quality assurance and engineering design usage. Any material specifications that the cell manufacturers use were developed for cosmetic reasons that have no technical basis. Therefore, the Applied Solar Energy Corporation (ASEC) has sponsored a continuing program for the fracture mechanics evaluation of GaAs. Fracture mechanics concepts were utilized to develop an analytical model that can predict the critical crack size of solar cells. This model indicates that the edge cracks of a solar cell are more critical than its surface cracks. In addition, the model suggests that the material specifications on the allowable crack size used for Si solar cells should not be applied to GaAs solar cells. The analytical model was applied to Si and GaAs solar cells, but it would also be applicable to the semiconductor wafers of other materials, such as a GaAs thin film on a Ge substrate, using appropriate input data.
A thin film SQUID is disclosed having improved flux concentration combined with simplicity of design and fabrication. The SQUID starts with a wafer like substrate having simple planar geometry. A large area of superconducting film is coated on the substrate, with a small open or uncoated area remaining at its center to define a SQUID loop, and a gap in the film formed, beginning at the outer circumferential edge of the substrate and extending radially inward to the open area. A Josephson junction is formed across the gap near the open area to interrupt the electrical continuity of the SQUID loop. A coil is attached to the surface of the substrate, electrically insulated from the superconducting film, and is energized to induce flux within the SQUID which is concentrated within the open area.
The paper describes a simple, safe, and effective method for forming shallow zinc-doped p-type layers on chromium-doped semiinsulating GaAs, using an open-tube diffusion technique. The resulting peak dopant concentration for the 850-C diffusion was 10 to the 20th/cu cm. The contact resistance of ohmic contacts fabricated on these layers was found to be about 0.00005 ohm/sq cm. The variation of the contact resistance across the wafer reflected the variation of the doping concentration.
The rapid thermal annealing (RTA) of indium phosphide (InP) substrates using a proximity contact method and silicon nitride encapsulation is investigated. The surface conditions of the InP substrates following cleaning with procedures A and B are analyzed. Procedure A involves using an iodic acid solution to remove work-damage InP surface layers and B is a degasssing process and hydrofluoric acid solution for native oxide removal. AES, XPS, and SIMS data of the proximity contact and silicon nitride encapsulated annealed samples are examined. The data reveal that RTA using proximity contact with silicon wafers does not provide adequate protection; however, the InP sample is successfully annealed when protected by a silicon nitride encapsulant.
p/n InP homojunction solar cells with a modified contacting scheme have been fabricated from wafers grown by liquid phase epitaxy. A p(+)-In(0.53)Ga(0.47)As contacting layer is incorporated in the cell structure to reduce contact resistance and to eliminaate surface spiking problems at the front surface. The highest conversion efficiency (total area) obtained under AM0 illumination is 15.0 percent. The corresponding open-circuit voltage, short-circuit current density, and fill factor for the best cell are 0.866 V, 29.3 mA/sq cm, and 81.0 percent, respectively.
In 1986 during the flat-plate solar array project, silicon solar cells 4.0 sq cm in area were fabricated at the Jet Propulsion Laboratory (JPL) with a conversion efficiency of 20.1 percent (AM1.5-global). Sixteen cells were processed with efficiencies measuring 19.5 percent (AM1.5 global) or better. These cells were produced using refined versions of conventional processing methods, aside from certain advanced techniques that bring about a significant reduction in a major mechanism (surface recombination) that limits cell efficiency. Wacker Siltronic p-type float-zone 0.18-ohm-cm wafers were used. Conversion efficiencies in this range have previously been reported by other researchers, but generally on much smaller (0.5 vs. 4.0 cm) devices which have undergone sophisticated and costly processing steps. An economic analysis is presented of the potential payoffs for this approach, using the Solar Array Manufacturing Industry Costing Standards (SAMICS) methodology. The process sequence used and the assumptions made for capturing the economies of scale are presented.
The grazing incidence reflectance of silicon carbide films produced by plasma-assisted chemical vapor deposition has been evaluated in the spectral region from 256 to 1216 A. The results show that reflectivities higher than conventional coatings can be obtained on coatings deposited both on silicon wafers and quartz substrates. Potential application of silicon carbide films for EUV astronomical instruments will be discussed.
Attention is given to the relevant criteria governing materials choice in the growth of IR optoelectronic bulk single crystals of III-V and II-VI alloy and I-III-VI2 compound types. The most important considerations concern the control of crystal purity, microstructural perfection, stoichiometry, and uniformity during crystal growth, as well as the control of surface properties in wafer fabrication. Specific examples are given to illustrate the problems encountered and their preferred solutions.
Monolithic diode grids have been fabricated on 2-cm square gallium-arsenide wafers with 1600 Schottky-barrier varactor diodes. Shorted diodes are detected with a liquid-crystal technique, and the bad diodes are removed with an ultrasonic probe. A small-aperture reflectometer that uses wavefront division interference was developed to measure the reflection coefficient of the grids. A phase shift of 70 deg with a 7-dB loss was obtained at 93 GHz when the bias on the diode grid was changed from -3 V to 1 V. A simple transmission-line grid model, together with the measured low-frequency parameters for the diodes, was shown to predict the measured performance over the entire capacitive bias range of the diodes, as well as over the complete reactive tuning range provided by a reflector behind the grid, and over a wide range of frequencies from 33 GHz to 141 GHz. This shows that the transmission-line model and the measured low-frequency diode parameters can be used to design an electronic beam-steering array and to predict its performance. An electronic beam-steering array made of a pair of grids using state-of-the-art diodes with 5-ohm series resistances would have a loss of 1.4 dB at 90 GHz.
Variable angle spectroscopic ellipsometry has been applied to a GaAs-AlGaAs multilayer structure to obtain a three-dimensional characterization, using repetitive measurements at several spots on the same sample. The reproducibility of the layer thickness measurements is of order 10 A, while the lateral dimension is limited by beam diameter, presently of order 1 mm. Thus, the three-dimensional result mainly gives the sample homogeneity. In the present case three spots were used to scan the homogeneity over 1 in of a wafer which had molecular-beam epitaxially grown layers. The thickness of the AlGaAs, GaAs, and oxide layers and the Al concentration varied by 1 percent or less from edge to edge. This result was confirmed by two methods of data analysis. No evidence of an interfacial layer was observed on top of the AlGaAs.
(111) GaAs layers have been grown epitaxially on (111) Si wafers, both on-axis as well as 3-deg off-axis towards the 1 -1 0 direction, using molecular-beam epitaxy. The grown layers have been characterized by scanning electron microscopy, X-ray diffraction, and transmission electron microscopy.
Raman scattering studies for a series of CVD-grown cubic SiC single-crystal films with film thickness from 600 A to 17 microns are discussed. The results suggest that the crystalline orientations of the Si substrate and the 3C-SiC film are the same. It is found that the Si 522/cm phonon from a Si wafer is enhanced in intensity by a factor of 2-3 due to a CVD overlayer of cubic SiC, and that the 3C-SiC longitudinal optical phonon at the Gamma point from SiC/Si samples is enhanced by a factor of two or three following the removal of the Si substrate. The variation of the Raman spectrum with incident power is investigated, and a method for determining the Raman cross section for 3 C-SiC is proposed.
Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.
A small CO2 snow cleaning apparatus to clean both molecular films and particles from small and large components and surfaces was constructed. Various types of surfaces were cleaned using the CO2 technique. Vacuum deposited and sputtered metallic coatings such as germanium, aluminum, and silver and silicon wafers, and polished copper conical mirrors were purposely contaminated with everyday aerospace contaminants, including particle fallout and fingerprints. Precleaning characterization by Bidirectional Reflectance Distribution Function (BRDF), ellipsometry, nonvolatile residue, and microscopic particle evaluation served as evaluation of cleaning efficiency. Good results were obtained in trial application.
The results of an experimental study of the reaction kinetics of silver with atomic oxygen in 10 degree increments over the temperature range of 0 to 70 C is reported. The silver specimens, of the order of 10,000 A in thickness, were prepared by thermal evaporation onto 3 inch diameter polished silicon wafers. There were later sliced into pieces having surface areas of the order of 1/4 to 1/2 square inch. Atomic oxygen was generated by a gas discharge in a commercial plasmod asher operating in the megahertz frequency range. The sample temperature within the chamber was controlled by means of a thermoelectric unit. Exposure of the silver specimens to atomic oxygen was incremental, with oxide film thickness measurements being carried out between exposures by means of an automated ellipsometer. For the early growth phase, the data can be described satisfactorily by a logarithmic growth law: the oxide film thickness increases as the logarithm of the exposure time. Furthermore, the oxidation process is thermally activated, the rate increasing with increasing temperature. However, the empirical activation energy parameter deduced from Arrhenius plots is quite low, being of the order of 0.1 eV.