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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,297 records · Page 72
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

Departure Queue Prediction for Strategic and Tactical Surface Scheduler Integration

A departure metering concept to be demonstrated at Charlotte Douglas International Airport (CLT) will integrate strategic and tactical surface scheduling components to enable the respective collaborative decision making and improved efficiency benefits these two methods of scheduling provide. This study analyzes the effect of tactical scheduling on strategic scheduler predictability. Strategic queue predictions and target gate pushback times to achieve a desired queue length are compared between fast time simulations of CLT surface operations with and without tactical scheduling. The use of variable departure rates as a strategic scheduler input was shown to substantially improve queue predictions over static departure rates. With target queue length calibration, the strategic scheduler can be tuned to produce average delays within one minute of the tactical scheduler. However, root mean square differences between strategic and tactical delays were between 12 and 15 minutes due to the different methods the strategic and tactical schedulers use to predict takeoff times and generate gate pushback clearances. This demonstrates how difficult it is for the strategic scheduler to predict tactical scheduler assigned gate delays on an individual flight basis as the tactical scheduler adjusts departure sequence to accommodate arrival interactions. Strategic/tactical scheduler compatibility may be improved by providing more arrival information to the strategic scheduler and stabilizing tactical scheduler changes to runway sequence in response to arrivals.

departure scheduling↗
NASA NTRS2017

Assessing Tactical Scheduler Options for Time-Based Surface Metering

NASA is committed to demonstrating a concept of integrated arrival, departure, and surface operations by 2020 under the Airspace Technology Demonstration 2 (ATD2) sub-project. This will be accomplished starting with a demonstration of flight specific time-based departure metering at Charlotte Douglass International Airport (CLT). ATD2 tactical metering capability is based on NASAs Spot And Runway Departure Advisor (SARDA) which has been tested successfully in human-in-the-loop simulations of CLT. SARDA makes use of surface surveillance data and surface modeling to estimate the earliest takeoff time for each flight active on the airport surface or ready for pushback from the gate. The system then schedules each flight to its assigned runway in order of earliest takeoff time and assigns a target pushback time, displayed to ramp controllers as an advisory gate hold time. The objective of this method of departure metering is to move as much delay as possible to the gate to minimize surface congestion and engine on-time, while keeping sufficient pressure on the runway to maintain throughput. This flight specific approached enables greater flight efficiency and predictability, facilitating trajectory-based operations and surface-airspace integration, which ATD2 aims to achieve.Throughout ATD2 project formulation and system development, researchers have continuously engaged with stakeholders and future users, uncovering key system requirements for tactical metering that SARDA did not address. The SARDA scheduler is updated every 10 seconds using real-time surface surveillance data to ensure the most up-to-date information is used to predict runway usage. However, rapid updates also open the potential for fluctuating advisories, which Ramp controllers at a busy airport like CLT find unacceptable. Therefore, ATD2 tactical metering requires that all advisories freeze once flights are ready so that Ramp controllers may communicate a single hold time when responding to pilot ready calls.

Zelinski, Shannon↗
NASA NTRS2018

One Time Programmable Antifuse Memory Based on Bulk Junctionless Transistor

One time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.

Antifuse↗
NASA NTRS2019

Validation of Proposed Go-Around Criteria Under Various Environmental Conditions

This paper evaluates the effects of environmental conditions on touchdown performance under varying approach states and validates proposed go-around criteria developed using data from a previously conducted study under these various environmental conditions. An experiment was conducted using Boeing 737-800 and Airbus A330-200 Level D full-flight simulators in which 24 pilots flew multiple approaches under different approach conditions and environmental variables. Pilots were instructed to always land the aircraft, even from conditions considered to be an unstable approach. Various touchdown performance metrics were analyzed. In addition, pilots’ perceptions of risk under the various unstable approach conditions and resulting landings were assessed. The results of the study revealed that wind speed/direction and visibility had a stronger effect on touchdown performance than the approach parameters. Specifically, wind had a highly significant effect on longitudinal and lateral touchdown point, as well as a significant effect on sink-rate at touchdown. Wind and visibility, along with localizer deviation, also had a strong effect on pilots’ perception of risk and workload ratings. Furthermore, the study confirmed that touchdown performance was similar among the runs with a 300-foot and 500-foot starting gate, as was found in the previously conducted experiment. These results support the previous finding that lowering the go-around decision gate to 300-foot might be acceptable, but suggest that certain environmental conditions might warrant altered thresholds of the proposed go-around criteria at this gate. Finally, the findings of this experiment highlight the importance of environmental factors in the assessment of risk of unwanted outcomes on approach and landing.

Transport Aircraft↗
NASA NTRS2019

Assessment of Ramp Times (ART 2) Human-In-The-Loop (HITL) Simulation - Final Results

Airspace Technology Demonstration 2 (ATD-2) sub-project conducted a human-in-the-loop (HITL) simulation to assess various strategies for Ramp controllers to deliver aircraft to the spot at a specified time. Results show that the rate of compliance with the spot time improved when Ramp controllers first complied with a gate hold advisory for pushing aircraft off the gates. Results also show that Ramp controller workload was lower when they only had to focus on complying with the gate hold advisories.

Stevens, Lindsay K.↗
NASA NTRS2019

Pilot Evaluation of Proposed Go-Around Criteria for Transport Category Aircraft

The primary objective of this study was to capture pilot feedback and decision-making with regard to proposed, hypothetical, go-around criteria that were developed based on previous research. A secondary objective of the study was to assess crew members' awareness of the aircraft state on approach. An experiment was conducted using Boeing 737-800 and Airbus A330-200 level D full-flight simulators, in which pilots flew multiple approaches which were on the borderline of the proposed go-around criteria at 300 ft. Pilots were instructed that they could either execute a go-around or land the airplane on each run, forcing a decision for the borderline cases at 300 ft. Pilots were instructed to go around if the aircraft was outside of the go-around criteria at 300 ft or if either pilot was uncomfortable with the approach. The results revealed that: 1) the most important factors which drove go-around decision-making during the experiment were airspeed and localizer deviation, 2) the objective data suggested that the 300-ft gate is viable, although many pilots were still uncomfortable with that gate height; perhaps more emphasis on checking stability at 1,000 ft and 500 ft would make more pilots comfortable with the 300-ft go-around gate, 3) allowing for momentary deviations should be considered, and 4) the acceptability of the criteria is highly dependent on given pilot's risk tolerance. Overall, the proposed criteria performed well, and most pilots would find the criteria acceptable with some minor adjustments.

go-arounds↗
NASA NTRSDate not supplied

Human Factors Impact of Different Ramp Controller Scheduling Advisories for ATD-2 Surface Metering in a Human-in-the-Loop Simulation

A human-in-the-loop (HITL) simulation took place in 2019 at NASA Ames Research Center’s Future Flight Central, an airport simulator with a full-scale 360-degree view that showed real-time airport operations at Dallas/Fort Worth International Airport (DFW). The HITL was part of the NASA/FAA Airspace Technology Demonstration 2 (ATD-2) project which involves an on-going field demonstration at Charlotte Douglas International Airport (CLT). In the field demonstration, metering on the airport surface takes place with one of the goals being to reduce runway queue length by holding aircraft at the gate during busy times, thereby reducing fuel burn and CO2 emissions. This goal has been successfully accomplished at CLT by showing Ramp Controllers when to release aircraft at the gate so as to reduce aircraft waiting in the queue. Among the questions that the current simulation at DFW was designed to address were, "Which types of advisories to the Ramp Controllers work best, those that show a ±2 minute window for a release time from the gate, or a ±5 minute window for an arrival time at the spot (where Air Traffic Control takes over) or both?" and "How do these different types of advisories affect Ramp Controller workload and situation awareness?" Another question was, “Does a ramp that is less restrictive than the one at CLT affect compliance with these advisories?”

Bonny K Parke↗
NASA NTRS2001

A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.

Green, M. L.↗
NASA NTRS2024

Two mechanisms for the spontaneous emergence, execution, and reprogramming of chemical logic circuits

A key question in origin-of-life research is how primitive life or life-like systems obtained reusable and reprogrammable machinery of processing information to respond to various environmental and internal stimuli. One strategy to approach this question is to view living systems as universal chemical computers. This approach focuses upon uncovering how reusable and reprogrammable chemical NOT, AND, and OR logic gates could appear under prebiotically possible scenarios where simple chemicals and second- or lower-order reactions are more frequent than macromolecules and higher-order reactions. In this article, we theoretically model two generic mechanisms of forming Boolean gates based on geochemically plausible reaction systems that could have preceded complex biopolymers. The mechanisms exploit simple bistable autocatalytic systems to encode binary variables and use heterogeneous dilution rates to differentially activate or deactivate autocatalysis in different reactors. We found that NOT, AND, and OR gates, as well as more complex logic circuits, can spontaneously arise from connected, well-mixed flow reactors based on (i) catalysis by a heterodimer between mutually inhibitory autocatalysts or (ii) selectively permeable tunnels connecting reactors. Our results suggest that simple machinery can support the prebiotic emergence of complex chemical logic circuits and provide new guides for experimentally actualizing chemical computation.

Zhen Peng↗
DOE OSTI2020

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗
DOE OSTI2021

Semiconductor topologies and devices for soft starting and active fault protection of power converters

Various examples are provided related to semiconductor topologies and devices that can be used for soft starting and active fault protection of power converters. In one example, an active switch device includes an active switch having a gating control input; and a thyristor having a gating control input. The thyristor is coupled in parallel with the active switch. The active switch can be an IGBT, MOSFET, or other appropriate device. In another example, a power converter can include the active switch devices and switching control circuitry coupled to gating control inputs of the active switch devices.

Beddingfield, Richard B.↗
DOE OSTI2022

Power MOSFET and JBSFET cell topologies with superior high frequency figure of merit

A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

Baliga, Bantval Jayant↗
DOE OSTI2023

Three dimensional vertically structured electronic devices

In one embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of three dimensional (3D) structures above the substrate, a gate region, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure. The gate region is present on a portion of an upper surface of the second region and the gate region is coupled to a portion of the at least one vertical sidewall of each 3D structure.

Conway, Adam↗
DOE OSTI2020

2D Dam-Break Analysis of L Lake and PAR Pond Dams Using HEC-RAS

In 1991 a dam-break study was conducted for the high hazard dams located at L Lake and PAR Pond on the Savannah River Site. Two scenarios were considered, over topping from a Probable Maximum Flood (PMF), and a fair weather dam-break for either or both dams. Unfortunately, no inundation map was developed from the study. The purpose of this project was to redo the original dam-break study with improved data and methodology to generate Inundation maps to assist with emergency response and evacuation plans. The Hydrologic Engineering Center's River Analysis System (HEC-RAS) is a free to download river analysis modeling program developed by the US Army Corps of Engineers capable of 1D and 2D hydraulic calculations. Version 5.0.7 (released March 2019) was used for this project. Digital elevation models for the area were retrieved from the US Geological Survey database and converted to a .hdf file within the program. Then the 2D flood area was identified from the contours. Both L Lake and PAR Pond were inputted as 1D storage areas because DEM data does not contain elevation values under water bodies. An elevation vs volume curve was available for both storage areas. Initial elevations were set for both scenarios. Both dams are earthen dams. The Steel Creek dam at L Lake has 6 ft diameter conduit with an upper and lower sluice gate. PAR pond dam consist of a weir and sluice gate connected to an 8 x 8 ft channel. Both outlets were modeled with a pool elevation vs discharge curve. The steel creek dam sluice gates were assumed to be fully open in all cases. As in the previous study, the dams were set to breach when they were overtopped by 1.5 ft during PMF conditions (Figure 1). A fair weather breach was set to be due to a piping failure (Figure 1). In the dual dam break during fair weather conditions the PAR pond dam fails 3 hours after Steel Creek to achieve maximum flooding in the down stream reaches. Simulation was run 3 days for each case and with a 1 minute computational interval. Maximum flooding occurs under PMF conditions with the failure of both dams. PAR pond dam fails first 16 hours and 32 minutes after the start of the simulation with the Steel creek dam failing 6 minutes later. In all cases, the bridges and roads spanning Steel Creek and Lower Three Runs will be inundated and potentially washed away. The Burtons Ferry Highway south of the storage areas will be partially flooded during PMF failure, dual fair weather failure, and PAR pond failure under fair weather conditions.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗
DOE OSTI2024

Simulating single qubit RB

Single qubit RB is used to measure the error of gates via average gate fidelity. A single qubit RB program was made to calculate this. To filter out potential hardware issues, RB was executed through creating a simulator. Upon simulating both noisy and noise-less gates, we determined that there is a mix of hardware and program issues.

Anguiano, Efren↗
DOE OSTI2024

Power Module Precursors and Prognostics

This project focuses on finding and utilizing electrical properties (precursors) of power electronic devices and modules whose changes have strong correlations with different modes and levels of degradations in order to realize online and lightweight state of health evaluation and fault diagnosis. Results from this project will contribute to higher safety, reliability, and power density of power electronic components. The approaches mainly include reviewing academic literature and industry practices for state of the art precursor identification and extraction, accelerated life cycles (ALC) of various power modules to create different degradations in-house, and developing techniques for gate-driver-integratable precursor detection circuit. In FY24, the results includes two sets of definitively detected aging precursors (on-state resistance and gate threshold voltage) for two sets of power modules respectively, controlled accelerated lifetime cycling of multiple silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) modules, and the development and validation of a gate voltage detection system.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2026

Universal monitored dynamics in multimode bosonic systems

We propose a route to study monitored many-body dynamics in multimode bosonic systems using circuit quantum electrodynamics. In this experimental setting, we construct several bosonic models comprising brickwork circuits built from beam-splitter gates, local parity measurements, and optional on-site Hubbard interactions, and diagnose their monitored dynamics via ancilla purification and a learnability-based probe. Under parity measurements, generic gate sets exhibit behavior that is largely consistent with a conventional measurement-induced phase transition, while a special class of beam-splitter circuits shows an apparent critical-like high-measurement regime in which purification times scale linearly with system size. We show that for realistic noise, gate, and measurement rates, these signatures are observable with near-term circuit QED hardware.

Patel, Shivam [Rutgers U., Piscataway]↗