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At least 1,279 records · Page 71
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

Test structures for propagation delay measurements on high-speed integrated circuits

The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.

Long, S. I.↗
NASA NTRS1985

Microhardness of carbon-doped (111) p-type Czochralski silicon

The effect of carbon on (111) p-type Czochralski silicon is examined. The preparation of the silicon and microhardness test procedures are described, and the equation used to determine microhardness from indentations in the silicon wafers is presented. The results indicate that as the carbon concentration in the silicon increases the microhardness increases. The linear increase in microhardness is the result of carbon hindering dislocation motion, and the effect of temperature on silicon deformation and dislocation mobility is explained. The measured microhardness was compared with an analysis which is based on dislocation pinning by carbon; a good correlation was observed. The Labusch model for the effect of pinning sites on dislocation motion is given.

Danyluk, S.↗
NASA NTRS1986

Solar-Cell-Junction Processing System

System under development reduces equipment costs. Processing system will produce solar-cell junctions on 4 in. (10.2 cm) round silicon wafers at rate of 10 to seventh power per year. System includes non-mass-analyzed ion implanter, microcomputer-controlled, pulsed-electron-beam annealer, and wafertransport system with vacuum interlock. These features eliminate large, expensive magnet and plates, circuitry, and power source otherwise needed for scanning.

Bunker, S. N.↗
NASA NTRS1986

Metalizing Solar Cells by Selective Electroplating

Contact patterns traced by laser scanning. Conductor paths deposited on silicon solar-cell wafers by laser irradiation followed by electroplating. Laser-assisted metalization technique offers better resolution and lower contact resistance than does conventional metalization by screen printing. At the same time, less expensive than metalization with masks and photolithography.

Dutta, S.↗
NASA NTRS1986

Crack Growth in Single-Crystal Silicon

Report describes experiments on crack growth in single-crystal silicon at room temperature in air. Crack growth in (111) cleavage plane of wafers, 50 by 100 by 0.76 mm in dimension, cut from Czochralski singlecrystal silicon studied by double-torsion load-relaxation method and by acoustic-emission measurements. Scanning electron microscopy and X-ray topography also employed. Results aid in design and fabrication of silicon photovoltaic and microelectronic devices.

Chen, C. P.↗
NASA NTRS1986

Filters for Submillimeter Electromagnetic Waves

New manufacturing process produces filters strong, yet have small, precise dimensions and smooth surface finish essential for dichroic filtering at submillimeter wavelengths. Many filters, each one essentially wafer containing fine metal grid made at same time. Stacked square wires plated, fused, and etched to form arrays of holes. Grid of nickel and tin held in brass ring. Wall thickness, thickness of filter (hole depth) and lateral hole dimensions all depend upon operating frequency and filter characteristics.

Berdahl, C. M.↗
NASA NTRS1986

Laser Vacuum Furnace for Zone Refining

Laser beam scanned to produce moving melt zone. Experimental laser vacuum furnace scans crystalline wafer with high-power CO2-laser beam to generate precise melt zone with precise control of temperature gradients around zone. Intended for zone refining of silicon or other semiconductors in low gravity, apparatus used in normal gravity.

Griner, D. B.↗
NASA NTRS1985

Materials requirements for high-efficiency silicon solar cells

To achieve higher Si solar cell efficiencies (greater than 20%), better single-crystal Si must be produced. It is believed possible to bring Cz (Czochralski) Si up to the same low recombination level as FZ (Float Zone) Si. It is also desirable that solar cell Si meet the following requirements: long minority carrier lifetime (0.2 ohm-cm p-type with tau less than 500 microsec); repeatedly uniform lifetime (not spread from 50 to 1000 microsec); a lifetime that does not decrease during normal device processing; a silicon wafer sheet that is flat and stays throughout normal device processing; uniform and reasonable mechanical strength; and, manufacture at low cost (less than $50/sq m).

Wolf, M.↗
NASA NTRS1985

The status of silicon ribbon growth technology for high-efficiency silicon solar cells

More than a dozen methods have been applied to the growth of silicon ribbons, beginning as early as 1963. The ribbon geometry has been particularly intriguing for photovoltaic applications, because it might provide large area, damage free, nearly continuous substrates without the material loss or cost of ingot wafering. In general, the efficiency of silicon ribbon solar cells has been lower than that of ingot cells. The status of some ribbon growth techniques that have achieved laboratory efficiencies greater than 13.5% are reviewed, i.e., edge-defined, film-fed growth (EFG), edge-supported pulling (ESP), ribbon against a drop (RAD), and dendritic web growth (web).

Ciszek, T. F.↗
NASA NTRS1985

Future application of Czochralski crystal pulling for silicon

Czochralski (Cz) crystal pulling has been the predominant method used for preparing silicon single crystal for the past twenty years. The fundamental technology used has changed little. However, great strides have been made in learning how to make the crystals bigger and of better quality at ever increasing productivity rates. Currently charge sizes of 50 kg of polycrystal silicon are being used for production and crystals up to ten inches in diameter have been grown without major difficulty. The largest material actually being processed in silicon wafer form is 150 mm (6 inches) in diameter. Growing of crystals in a magnetic field has proved to be particularly useful for microscopic impurity control. Major developments in past years on equipment for Cz crystal pulling have included the automatic growth control of the diameter as well as the starting core of the crystal, the use of magnetic fields and around the crystal puller to supress convection, various recharging schemes for dopant control and the use of continuous liquid feed in the crystal puller. The latter, while far from being a reliable production process, is ideal in concept for major improvement in Cz crystal pulling. The Czochralski process will maintain its dominance of silicon crystal production for many years.

Matlcok, J. H.↗
NASA NTRS1985

New outlook on control of crystalline and chemical perfection during growth of silicon

Significant progress has been made in our understanding of the Czochralski crystal growth process with the realization that the incorporation of oxygen into silicon is directly related to the internal gettering capability of wafers during device fabrication. It was also recognized that the electronic properties exhibited by silicon during various stages of device fabrication were significantly affected by the thermal history of the silicon during the post-growth cool-down period. Turbulent melt convection, induced by unavoidable destabilizing thermal gradients, was found to interfere with homogeneous dopant (and oxygen) incorporation and to influence markedly the dynamics of nonequilibrium point defects in the solidified silicon matrix during the cool-down period. In view of the unavoidability of destabilizing thermal gradients in conventional crystal growth configurations, melt stabilization through the application of magnetic fields is generally considered a viable approach. Control of heat input to the melt through heat pipe systems, as used during growth of germanium, cannot be applied to industrial growth of silicon. Recent studies have shown that heat exchange systems located coaxially about a growing crystal can be used to stabilize and control not only heat transfer in the grown crystal, but also in the melt adjacent to the solidification interface.

Witt, A. F.↗
NASA NTRS1985

Oxygen and carbon in silicon

The properties of the early transistors were determined by the minority-carrier lifetime, as is the silicon photovoltaic solar cell. Most of the devices on the modern integrated circuits are majority carrier devices, in part to avoid this lifetime dependence. The micro-electronics industry typically starts with wafers with a minority-carrier lifetime of 1000 micro-seconds, but during device fabrication this lifetime is reduced to beflow 1 micro-second, in spite of extraordinary cleanliness and precautions. Process-induced defects (PID) include point defects, defect complexes, line defects, and bulk precipitates. One of the aspects that needs to be better understood is the nature of minority carrier recombination at line defects and at precipitates. Some of the PIDs are known to be related to the fast-diffusers of the iron-series transition elements. One of the common techniques of dealing with these elements is intrinsic gettering by the oxygen precipitates. But even in the gettered state, there may be a residual effect on the lifetime. Oxygen is an almost ubiquitous impurity in silicon and plays an important role in both integrated circuits and solar cells. The isolated oxygen interstitial is electrically inactive, but in its various aggregated forms it has a variety of electrical activities. The agglomeration and precipitation of oxygen, including impurity gettering and the complicating role of carbon, is discussed.

Corbett, J. W.↗
NASA NTRS1986

A metallurgical route to solar-grade silicon

The aim of the process is to produce silicon for crystallization into ingots that can be sliced to wafers for processing into photovoltaic cells. If the potential purity can be realized, the silicon will also be applicable for ribbon pulling techniques where the purification during crystallization is negligible. The process consists of several steps: selection and purification of raw materials, carbothermic reduction of silica, ladle treatment, casting, crushing, leaching, and melting. The leaching step is crucial for high purity, and the obtainable purity is determined by the solidification before leaching. The most difficult specifications to fulfill are the low contents of boron, phosphorus, and carbon. Boron and phosphorus can be excluded from the raw materials, but the carbothermic reduction will unavoidably saturate the silicon with carbon at high temperature. During cooling carbon will precipitate as silicon carbide crystals, which will be harmful in solar cells. The cost of this solar silicon will depend strongly on the scale of production. It is as yet premature to give exact figures, but with a scale of some thousand tons per year, the cost will only be a few times the cost of ordinary metallurgical silicon.

Schei, A.↗
NASA NTRS1986

Characterization of solar-grade silicon produced by the SiF4-Na process

A process was developed for producing low cost solar grade silicon by the reaction between SiF4 gas and sodium metal. The results of the characterization of the silicon are presented. These results include impurity levels, electronic properties of the silicon after crystal growth, and the performance of solar photovoltaic cells fabricated from wafers of the single crystals. The efficiency of the solar cells fabricated from semiconductor silicon and SiF4-Na silicon was the same.

Sanjurjo, A.↗
NASA NTRS1984

Space station automation study: Automation requriements derived from space manufacturing concepts,volume 2

Automation reuirements were developed for two manufacturing concepts: (1) Gallium Arsenide Electroepitaxial Crystal Production and Wafer Manufacturing Facility, and (2) Gallium Arsenide VLSI Microelectronics Chip Processing Facility. A functional overview of the ultimate design concept incoporating the two manufacturing facilities on the space station are provided. The concepts were selected to facilitate an in-depth analysis of manufacturing automation requirements in the form of process mechanization, teleoperation and robotics, sensors, and artificial intelligence. While the cost-effectiveness of these facilities was not analyzed, both appear entirely feasible for the year 2000 timeframe.

Source record↗
NASA NTRS1985

Pinhole array capacitor for oxide integrity analysis

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk process. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Buehler, M. G.↗
NASA NTRS1985

JMOSFET: A MOSFET parameter extractor with geometry-dependent terms

The parameters from metal-oxide-silicon field-effect transistors (MOSFETs) that are included on the Combined Release and Radiation Effects Satellite (CRRES) test chips need to be extracted to have a simple but comprehensive method that can be used in wafer acceptance, and to have a method that is sufficiently accurate that it can be used in integrated circuits. A set of MOSFET parameter extraction procedures that are directly linked to the MOSFET model equations and that facilitate the use of simple, direct curve-fitting techniques are developed. In addition, the major physical effects that affect MOSFET operation in the linear and saturation regions of operation for devices fabricated in 1.2 to 3.0 mm CMOS technology are included. The fitting procedures were designed to establish single values for such parameters as threshold voltage and transconductance and to provide for slope matching between the linear and saturation regions of the MOSFET output current-voltage curves. Four different sizes of transistors that cover a rectangular-shaped region of the channel length-width plane are analyzed.

Buehler, M. G.↗