Overview on plasma operation with a full tungsten wall in ASDEX Upgrade
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We present a programmable time alignment scheme used in an ASIC for the ATLAS forward muon trigger development. The scheme utilizes regenerated clocks with programmable phases to compensate for the timing offsets introduced by different detector trace lengths. Each ASIC used in the design has 104 input channels with delay compensation circuitry providing steps of ~ 3 ns and a full range of 25 ns for each channel. Detailed implementation of the scheme including majority logic to suppress single-event effects is presented. The scheme is flexible and fully synthesizable. Here, the approach is adaptable to other applications with similar phase shifting requirements. In addition, the design is resource efficient and is suitable for cost-effective digital implementation with a large number of channels.
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The Cathode Strip Chamber (CSC) is the primary system for muon detection in the CMS endcap region. Starting in 2026 both the instantaneous luminosity and CMS level 1 latency will be increased significantly, which will exceed the design specifications of the CSC electronics. The large integrated particle flux also increases the potential for chamber aging and performance degradation. This paper presents the studies of CSC electronics and CSC longevity performed at the CERN GIF++ facility.