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Results for “PROCESSOR”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Modeling and Characterizing Noise in Quantum Processors.
Abstract not provided.
Accelerating scale-up of quantum processors with split accumulation gate quantum dots.
Abstract not provided.
Computational processor-in-memory with enhanced strided memory access
A computational memory for a computer. The memory includes a memory bank having a selected-row buffer and being configured to store records up to a number, K. The memory also includes an accumulator connected to the memory bank, the accumulator configured to store up to K records. The memory also includes an arithmetic and logic unit (ALU) connected to the accumulator and to the selected row buffer of the memory bank, the ALU having an indirect network of 2K ports for reading and writing records in the memory bank and the accumulator, and the ALU further physically configured to operate as a sorting network. The memory also includes a controller connected to the memory bank, the ALU, and the accumulator, the controller being hardware configured to direct operation of the ALU.
Arrangements for communicating data in a computing system using multiple processors
Systems and methods for reducing data movement in a computer system. The systems and methods use information or knowledge about the structure of an algorithm, operations to be executed at a receiving processing unit, variables or subsets or groups of variables in a distributed algorithm, or other forms of contextual information, for reducing the number of bits transmitted from at least one transmitting processing unit to at least one receiving processing unit or storage device.
Whetstone: An accessible platform-independent method training spiking deep neural networks for neuromorphic processors.
Abstract not provided.
Whetstone: An Accessible Platform-Independent Method for Training Spiking Deep Neural Networks for Neuromorphic Processors.
Abstract not provided.
Trinity Update: Open Science Burst Buffers Intel Xeon Phi Processor Plans.
Abstract not provided.
Multiscale Modeling of Single Event-Induced Faults in FinFET-based Processors.
Abstract not provided.
Fault Tracking and Modeling in Advanced Node Processors of Single Event Effects.
Abstract not provided.
Wildcard Error: Quantifying unmodeled errors in quantum processors.
Abstract not provided.
Runtime localized cooling of high-performance processors
A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.
Automated Calibration, characterization and optimization of near term quantum processors (Phase I Final Report)
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