SEARCH · Engineering Papers

Results for “GaTe”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,261 records · Page 70

All sources NASA NTRS DOE OSTI

NASA NTRS1990

The beam filling error in the Nimbus 5 electronically scanning microwave radiometer observations of Global Atlantic Tropical Experiment rainfall

A comparison of rain rates retrieved from the Nimbus 5 electronically scanning microwave radiometer brightness temperatures and observed from shipboard radars during the Global Atlantic Tropical Experiment (GATE) phase I shows that the beam filling error is the major source of discrepancy between the two. When averaged over a large scene (the GATE radar array, 400 km in diameter), the beam filling error is quite stable, being 50 percent of the observed rain rate. This suggests the simple procedure of multiplying retrieved rain rates by 2 (correction factor). A statistical model of the beam filling error is developed by envisioning an idealized instrument field-of-view that encompasses an entire gamma distribution of rain rates. A modeled correction factor near 2 is found for rain rate and temperature characteristics consistent with GATE conditions. The statistical model also suggests that the correction factor varies from 1.5 to 2.5 for suppressed to enhanced tropical convective regimes, and decreases to 1.5 as the freezing level and average depth of the rain column decreases to 2.5 km.

Short, David A.↗

NASA NTRS1990

Simplified calculation of wave-coupling between lines in high-speed integrated circuits

The construction of time-domain solutions by the superposition of modes is explained for the general case, which may not have any symmetry in the lines or terminations. This simplified method requires that the logic-gate terminal impedances be approximated by linear effective resistances that can be adequately determined by SPICE analysis of the actual logic gates. Several examples of results of crosstalk calculations made by the simplified method are presented and compared with corresponding results obtained using the SPICE transmission-line methods of Tripathi and Rettig (1985) along with full SPICE models of the logic gates. The simplified approach is shown to give satisfactory agreement for most purposes.

Matthaei, George L.↗

NASA NTRS1991

Report on the formal specification and partial verification of the VIPER microprocessor

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

Brock, Bishop↗

NASA NTRS1991

Depth-size tradeoffs for neural computation

The tradeoffs between the depth (i.e., the time for parallel computation) and the size (i.e., the number of threshold gates) in neural networks are studied. The authors focus the study on the neural computations of symmetric Boolean functions and some arithmetic functions. It is shown that a significant reduction in the size is possible for symmetric functions and some arithmetic functions, at the expense of a small constant increase in depth. In the process, several neural networks which have the minimum size among all the known constructions have been developed. Results on implementing symmetric functions can be used to improve results about arbitrary Boolean functions. In particular, It is shown that any Boolean function can be computed in a depth-3 neural network with O(2n/2) threshold gates; it is also proven that a minimum number of threshold gates are required.

Siu, Kai-Yeung↗

NASA NTRS1991

A high efficiency Ka-band monolithic pseudomorphic HEMT amplifier

A monolithic three-stage Ka-band amplifier has been designed and fabricated on a doped channel heterostructure. Devices with gate length of 0.2 micron and gate width of 50, 100, and 250 micron were cascaded. The gate and drain bias networks were also integrated. The small signal gain is 31 dB and the amplifier is capable of an output power of 190 mW with 23 dB gain and 30.2 percent power added efficiency at 31 GHz. This is a record efficiency for a multistage MMIC at this frequency.

Saunier, Paul↗

NASA NTRS1993

Application of high-quality SiO2 grown by multipolar ECR source to Si/SiGe MISFET

A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.

Sung, K. T.↗

NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗

NASA NTRS1990

High performance pipelined multiplier with fast carry-save adder

A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

Wu, Angus↗

NASA NTRS1994

Characteristics of III-V Semiconductor Devices at High Temperature

This paper presents the development of III-V based pseudomorphic high electron mobility transistors (PHEMT's) designed to operate over the temperature range 77 to 473 K (-196 to 200 C). These devices have a pseudomorphic undoped InGaAs channel that is sandwiched between an AlGaAs spacer and a buffer layer; gate widths of 200, 400, 1600, and 3200 micrometers; and a gate length of 2 micrometers. Measurements were performed at both room temperature and 473 K (200 C) and show that the drain current decreases by 30 percent and the gate current increases to about 9 microns A (at a reverse bias of -1.5 V) at the higher temperature. These devices have a maximum DC power dissipation of about 4.5 W and a breakdown voltage of about 16 V.

Simons, Rainee N.↗

NASA NTRS1995

AMCC casting development, volume 2

PCC successfully cast and performed nondestructive testing, FPI and x-ray, on seventeen AMCC castings. Destructive testing, lab analysis and chemical milling, was performed on eleven of the castings and the remaining six castings were shipped to NASA or Aerojet. Two of the six castings shipped, lots 015 and 016, were fully processed per blueprint requirements. PCC has fully developed the gating and processing parameters of this part and feels the part could be implemented into production, after four more castings have been completed to ensure the repeatability of the process. The AMCC casting has been a technically challenging part due to its size, configuration, and alloy type. The height and weight of the wax pattern assembly necessitated the development of a hollow gating system to ensure structural integrity of the shell throughout the investment process. The complexity in the jacket area of the casting required the development of an innovative casting technology that PCC has termed 'TGC' or thermal gradient control. This method of setting up thermal gradients in the casting during solidification represents a significant process improvement for PCC and has been successfully implemented on other programs. The alloy, JBK75, is a relatively new alloy in the investment casting arena and required our engineering staff to learn the gating, processing, and dimensional characteristics of the material.

Source record↗

NASA NTRS1998

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

Duen Ho, Fat↗

NASA NTRS1999

I-V Characteristics of a Ferroelectric Field Effect Transistor

There are many possible uses for ferroelectric field effect transistors.To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a field effect transistor are described. The effective gate capacitance and charge are derived from experimental data on an actual FFET. The general equation for a MOSFET is used to derive the internal characteristics of the transistor: This equation is modified slightly to describe the FFET characteristics. Experimental data derived from a Radiant Technologies FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations. The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material in the transistor. Two different polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse.

MacLeod, Todd C.↗

NASA NTRS2001

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Bell, L. D.↗

NASA NTRS2001

NASA/University JOint VEnture (JOVE) Program: Transverse Shear Moduli Using the Torsional Responses of Rectangular Laminates

The first year included a study of the non-visible damage of composite overwrapped pressure vessels with B. Poe of the Materials Branch of Nasa-Langley. Early determinations showed a clear reduction in non-visible damage for thin COPVs when partially pressurized rather than unpressurized. Literature searches on Thicker-wall COPVs revealed surface damage but clearly visible. Analysis of current Analytic modeling indicated that that current COPV models lacked sufficient thickness corrections to predict impact damage. After a comprehensive study of available published data and numerous numerical studies based on observed data from Langley, the analytic framework for modeling the behavior was determined lacking and both Poe and Bogan suggested any short term (3yr) result for Jove would be overly ambitious and emphasis should be placed on transverse shear moduli studies. Transverse shear moduli determination is relevant to the study of fatigue, fracture and aging effects in composite structures. Based on the techniques developed by Daniel & Tsai, Bogan and Gates determined to verify the results for K3B and 8320. A detailed analytic and experimental plan was established and carried out that included variations in layup, width, thickness, and length. As well as loading rate variations to determine effects and relaxation moduli. The additional axial loads during the torsion testing were studied as was the placement of gages along the composite specimen. Of the proposed tasks, all of tasks I and 2 were completed with presentations given at Langley, SEM conferences and ASME/AIAA conferences. Sensitivity issues with the technique associated with the use of servohydraulic test systems for applying the torsional load to the composite specimen limited the torsion range for predictable and repeatable transverse shear properties. Bogan and Gates determined to diverge on research efforts with Gates continuing the experimental testing at Langley and Bogan modeling the apparent non-linear behavior at low torque & angles apparent from the tests.

Bogan, Sam↗

NASA NTRS2001

Quantum Mechanical Study of Nanoscale MOSFET

The steady state characteristics of MOSFETS that are of practical Interest are the drive current, off-current, dope of drain current versus drain voltage, and threshold voltage. In this section, we show that quantum mechanical simulations yield significantly different results from drift-diffusion based methods. These differences arise because of the following quantum mechanical features: (I) polysilicon gate depletion in a manner opposite to the classical case (II) dependence of the resonant levels in the channel on the gate voltage, (III) tunneling of charge across the gate oxide and from source to drain, (IV) quasi-ballistic flow of electrons. Conclusions dI/dV versus V does not increase in a manner commensurate with the increase in number of subbands. - The increase in dI/dV with bias is much smaller then the increase in the number of subbands - a consequence of bragg reflection. Our calculations show an increase in transmission with length of contact, as seen in experiments. It is desirable for molecular electronics applications to have a small contact area, yet large coupling. In this case, the circumferential dependence of the nanotube wave function dictates: - Transmission in armchair tubes saturates around unity - Transmission in zigzag tubes saturates at two.

Svizhenko, Alexei↗

NASA NTRS2002

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Robert L Shuler, Jr.↗

NASA NTRS2002

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Robert L Shuler Jr.↗

NASA NTRS2003

Physiological Maturation of Regenerating Hair Cells

The bullfrog saccule, a sensor of gravity and substrate-borne vibration, is a model system for hair cell transduction. Saccular hair cells also increase in number throughout adult life and rapidly recover after hair cell damage, making this organ an ideal system for studying hair cell development, repair, and regeneration. We have used of hair cell and supporting cell immunocytochemical markers to identify damaged hair cells and hair cell precursors in organotypic cultures of the bullfrog saccule. We then used an innovative combination of confocal, electron, and time-lapse microscopy to study the fate of damaged hair cells and the origin of new hair cells after gentamicin ototoxicity in normal and mitotically blocked saccular cultures. These studies have shown that gentamicin ototoxicity produces both lethal and sublethal hair cell damage. They have also shown that hair cell recovery in this organ takes place by both the repair of sublethally damaged hair cells and by the replacement of lost hair cells by mitotic regeneration. In parallel studies, we have used biophysical and molecular biological techniques to study the differentiation and innervation of developing, repairing, and regenerating hair cells. More specifically, we have used RT-PCR to obtain the bullfrog homologues of L-type voltage- gated calcium (L-VGCC) and large-conductance Ca(2+)-activated potassium (BK) channel genes. We have then obtained probes for these genes and, using in situ hybridization, begun to examine their expression in the bullfrog saccule and amphibian papilla. We have also used fluorescent-labeled channel toxins and channel toxin derivatives to determine the time of appearance of L-type voltage-gated calcium (L-VGCC) and Ca(2+)-activated potassium (BK) channels and to study dynamic changes in the number, distribution, and co-localization of these proteins in developing, repairing, and regenerating hair cells. Using time-lapse microscopy, we are also studying the dynamic relationship between ion channel clustering and synaptic formation in hair cells and afferent neurons. In future studies, we will determine when hair cell precursors acquire electrical tuning, and, using whole-cell patch-clamp techniques, identify and characterize their L-VGCC and BK currents. We will also use biophysical techniques to determine the number of L-VGCC and BK channels and the size and gating kinetics of their underlying L-VGCC and BK conductances, correlating these variables with the amplitude and frequency of membrane oscillations produced by intracellular current steps. We expect these studies to determine how hair cells regulate ion channel expression to achieve specific physiological responses.

Baird, Richard A.↗