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Special lead-forming tool puts step in leads of microwave power transistors without damaging braze joints that fasten leads to package. Stepped leads are soldered to circuit boards more reliably than straight leads, and stress on brazes is relieved. Lead-forming hand-tool has two parts: a forming die and an actuator. Spring-loaded saddle is adjusted so that when transistor package is placed on it, leads rest on forming rails.
A large scale integration (LSI) technology, the standard transistor array uses a prefabricated understructure of transistors and a comprehensive library of digital logic cells to allow efficient fabrication of semicustom digital LSI circuits. The cell placement technique for this technology involves formation of a one dimensional cell layout and "folding" of the one dimensional placement onto the chip. It was found that, by use of various folding methods, high quality chip layouts can be achieved. Methods developed to measure of the "goodness" of the generated placements include efficient means for estimating channel usage requirements and for via counting. The placement and rating techniques were incorporated into a placement program (CAPSTAR). By means of repetitive use of the folding methods and simple placement improvement strategies, this program provides near optimum placements in a reasonable amount of time. The program was tested on several typical LSI circuits to provide performance comparisons both with respect to input parameters and with respect to the performance of other placement techniques. The results of this testing indicate that near optimum placements can be achieved by use of the procedures incurring severe time penalties.
Transistors are characterized for use as switches in resonant circuit applications. A base drive circuit to provide the optimal base drive to these transistors under resonant circuit conditions is developed and then used in the design, fabrication and testing of a breadboard, spaceborne type 10 kW series resonant converter.
Improved switching transistors handle 400-A peak currents and up to 1,200 V. Using large diameter silicon wafers with twice effective area as D60T, form basis for D7 family of power switching transistors. Package includes npn wafer, emitter preform, and base-contact insert. Applications are: 25to 50-kilowatt high-frequency dc/dc inverters, VSCF converters, and motor controllers for electrical vehicles.
Vibration analyis is nondestructive and noninvasive. Transistor isolated from heat (or cold) of surroundings by filament suspension. Filaments made of polyester are (0.005 in) 0.127 mm in diameter. Transistor lead wires are wrapped around certain filaments. Applicable for testing filament mounts too delicate for testing by tension probes.
Indium solder boosts power rating and facilitates circuit changes. Efficient heat conduction from power transistor to heat sink provided by layer of indium solder. Low melting point of indium solder (141 degrees C) allows power transistor to be removed, if circuit must be reworked, without disturbing other components mounted with ordinary solder that melts at 181 degrees C. Solder allows devices operated at higher power levels than does conventional attachment by screws.
Boiling refrigerant provides simple temperature control for newly manufactured power transistors. Heat-transfer liquid is Fluorinert FC-77 (or equivalent). Liquid boils at 100 degrees C, which is specified temperature at which transistor cases should be maintained during burn-in with this technique.
Conceptual transistor embedded in photovoltaic diode promises to increase efficiency to more than 20 percent. Solar-cell transistor has front-surface contact, rear contact, and floating emitter. Variety of other contact and junction configurations possible, but do not offer ease of fabrication in combination with high performance.
A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.
This report describes the low-temperature transistor modules designed for use with the MSFC mid-infrared array. The modules were developed in the Space Science Laboratory at Marshall Space Flight Center with Center Director's Discretionary Funds. The transistors (JFETs), which operate at a temperature of 77 K, are epoxied to a copper surface attached to a Teflon substrate. The module substrate insulates the JFETs from the 1.5K detector work surfaces and provides a convenient mounting structure for additional components such as solder pins. These modules have maintained their structural integrity during repeated temperature cycling, and they have to be convenient during maintenance and servicing of the infrared array.
The D60T, D62T, and D75T transistors in the nuclear reactor were irradiated with bias voltage and high current I sub c vs. V sub ec curves were obtained to evaluate gain degradation at high power levels. Pre- and post-irradiation high current switching tests were performed to evaluate the response. The gamma ray damage work done at Sandia was correlated with the neutron work done at the O.S.U. reactor with the above specified transistors. Theoretical analyses of damage and electrical performance were conducted in terms of semiconductor physics. The experimental high current pulser was improved in order to measure switching time changes which are less than one microsecond at currents of 100 to 200 amperes for in-situ testing.
Equivalent base resistance added. Theoretical study develops equations for parameters of Gummel-Poon model of bipolar junction transistor: includes saturation current, amplification factors, charging times, knee currents, capacitances, and resistances. Portion of study concerned with base region goes beyond Gummel-Poon analysis to provide more complete understanding of transistor behavior. Extended theory useful in simulation of single-event upset (SEU) caused in logic circuits by cosmic rays or other ionizing radiation.
The use of nuclear reactors to generate electrical power for future space missions will require the electrical components used in the power conditioning, control, and transmission subsystem to operate in the associated radiation environments. An initial assessment of neutron irradiation on the electrical and switching characteristics of commercial high power NPN bipolar transistors was investigated. The results clearly show the detrimental effects caused by neutron irradiation on the electrical and switching characteristics of the NPN bipolar power transistor.
Quarter-micrometer gate-length high-electron-mobility transistors (HEMTs) for cryogenic low-noise application with very low light sensitivity have been developed. At room temperature, these exhibit a noise figure of 0.4 dB with associated gain of 15 dB at 8 GHz. At a temperature of 12.5 K the minimum noise temperature of 5.3 +/- 1.5 K has been measured at 8.5 GHz, which is the best noise performance observed to date for any microwave transistors. The results clearly demonstrate the potential for low-temperature low-noise applications.
A novel contact regrowth technique for the formation of extremely low nonalloyed ohmic contacts is reported. The successful demonstration of this technique is reported on an InGaAs/InAlAs hot-electron transistor device. For the investigated InGaAs-based structure, the regrown contacting scheme reported includes an In(0.53)Ga(0.47)As layer, an InAs/GaAs strained-layer superlattice, and an InAs cap, all heavily doped n type with Si. A very low specific contact resistance of 1.8 x 10 to the -7th ohm sq cm to the base layer is obtained. The higher current densities achieved in the transistor characteristics are in close agreement with calculations, and a contact model is presented explaining the poor results of conventional nonalloyed contacts.
Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
Simple configuration for wiring of multiple parallel-connected switching transistors minimizes stray wiring inductance while providing for use of balancing transformers, which equalize currents in transistors. Currents balanced on twisted pairs of wires. Because twisted pairs carry both "hot-side" and return currents, this configuration has relatively low inductance.
Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.