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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Improved performance of a digital phase-locked loop combined with a frequency/frequency-rate estimator

When a digital phase-locked loop with a long loop update time tracks a signal with high Doppler, the demodualtion losses due to frequency mismatch can become very significant. One way of reducing these Doppler-related losses is to compensate for the Doppler effect using some kind of frequency-rate estimator. The performance of the fixed-window least-squares estimator and the Kalman filter is investigated; several Doppler compensating techniques are proposed. It is shown that the variance of the frequency estimator can be made as small as desired, and with this, the Doppler effect can be effectively compensated. The remaining demodulation losses due to phase jitter in the loop can be less than 0.1 dB.

Mileant, A.↗
NASA NTRS1988

Digital phase-lock loop having an estimator and predictor of error

A digital phase-lock loop (DPLL) which generates a signal with a phase that approximates the phase of a received signal with a linear estimator. The effect of a complication associated with non-zero transport delays related to DPLL mechanization is then compensated by a predictor. The estimator provides recursive estimates of phase, frequency, and higher order derivatives, while the predictor compensates for transport lag inherent in the loop.

Statman, Joseph I.↗
NASA NTRS1973

A Computer Model of a Phase Lock Loop

A computer model is reported of a PLL (phase-lock loop), preceded by a bandpass filter, which is valid when the bandwidth of the bandpass filter is of the same order of magnitude as the natural frequency of the PLL. New results for the PLL natural frequency equal to the bandpass filter bandwidth are presented for a second order PLL operating with carrier plus noise as the input. However, it is shown that extensions to higher order loops, and to the case of a modulated carrier are straightforward. The new results presented give the cycle skipping rate of the PLL as a function of the input carrier to noise ratio when the PLL natural frequency is equal to the bandpass filter bandwidth. Preliminary results showing the variation of the output noise power and cycle skipping rates of the PLL as a function of the loop damping ratio for the PLL natural frequency equal to the bandpass filter bandwidth are also included.

Shelton, Ralph Paul↗
NASA NTRS1979

Loran digital phase-locked loop and RF front-end system error analysis

An analysis of the system performance of the digital phase locked loops (DPLL) and RF front end that are implemented in the MINI-L4 Loran receiver is presented. Three of the four experiments deal with the performance of the digital phase locked loops. The other experiment deals with the RF front end and DPLL system error which arise in the front end due to poor signal to noise ratios. The ability of the DPLLs to track the offsets is studied.

Mccall, D. L.↗
NASA NTRS1991

Steady-state phase error for a phase-locked loop subjected to periodic Doppler inputs

The performance of a carrier phase locked loop (PLL) driven by a periodic Doppler input is studied. By expanding the Doppler input into a Fourier series and applying the linearized PLL approximations, it is easy to show that, for periodic frequency disturbances, the resulting steady state phase error is also periodic. Compared to the method of expanding frequency excursion into a power series, the Fourier expansion method can be used to predict the maximum phase error excursion for a periodic Doppler input. For systems with a large Doppler rate fluctuation, such as an optical transponder aboard an Earth orbiting spacecraft, the method can be applied to test whether a lower order tracking loop can provide satisfactory tracking and thereby save the effect of a higher order loop design.

Chen, C.-C.↗
NASA NTRS1977

Simulation of digital phase-locked loops

Simulation equations are developed for first and second order digital phase locked loops. Examples of loop simulation are given to determine loop performance with respect to several loop parameters.

Blasche, P. R.↗
NASA NTRS1986

A class of optimum digital phase locked loops

This paper presents a class of optimum digital filters for digital phase locked loops, for the important case in which the maximum update rate of the loop filter and numerically controlled oscillator (NCO) is limited. This case is typical when the loop filter is implemented in a microprocessor. In these situations, pure delay is encountered in the loop transfer function and thus the stability and gain margin of the loop are of crucial interest. The optimum filters designed for such situations are evaluated in terms of their gain margin for stability, dynamic error, and steady-state error performance. For situations involving considerably high phase dynamics an adaptive and programmable implementation is also proposed to obtain an overall optimum strategy.

Kumar, R.↗
NASA NTRS1990

Demonstration of a low bandwidth 1.06-micron optical phase-locked loop for coherent homodyne communication

A type II 1.06-micron optical phase-locked loop (OPLL) for use in a coherent homodyne receiver is discussed. Diode-laser-pumped solid-state lasers are used for both the local oscillator and transmitter, because their phase noise is significantly lower than that of diode lasers. Closed-loop RMS phase noise of less than 12 mrad (0.69 deg) is achieved, and modulation-demodulation in bulk modulators at rates from 20 kHz to 20 MHz with less than 19 deg of modulation depth is demonstrated.

Day, T.↗
NASA NTRS1988

Designing Estimator/Predictor Digital Phase-Locked Loops

Signal delays in equipment compensated automatically. New approach to design of digital phase-locked loop (DPLL) incorporates concepts from estimation theory and involves decomposition of closed-loop transfer function into estimator and predictor. Estimator provides recursive estimates of phase, frequency, and higher order derivatives of phase with respect to time, while predictor compensates for delay, called "transport lag," caused by PLL equipment and by DPLL computations.

Statman, J. I.↗
NASA NTRS1992

Application of multirate digital filter banks to wideband all-digital phase-locked loops design

A new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity for hardware-processing speed by introducing parallel processing in the receiver. It is demonstrated here that the DPLL performance is identical to that of a PDPLL for both steady-state and transient behavior. A test signal with a time-varying Doppler characteristic is used to compare the performance of both the DPLL and the PDPLL.

Sadr, R.↗
NASA NTRS1993

Application of multirate digital filter banks to wideband all-digital phase-locked loops design

A new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity for hardware-processing speed by introducing parallel processing in the receiver. It is demonstrated here that the DPLL performance is identical to that of a PDPLL for both steady-state and transient behavior. A test signal with a time-varying Doppler characteristic is used to compare the performance of both the DPLL and the PDPLL.

Sadr, Ramin↗