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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

Lin, Shu↗
NASA NTRS1991

Combinatorial FSK modulation for power-efficient high-rate communications

Deep-space and satellite communications systems must be capable of conveying high-rate data accurately with low transmitter power, often through dispersive channels. A class of noncoherent Combinatorial Frequency Shift Keying (CFSK) modulation schemes is investigated which address these needs. The bit error rate performance of this class of modulation formats is analyzed and compared to the more traditional modulation types. Candidate modulator, demodulator, and digital signal processing (DSP) hardware structures are examined in detail. System-level issues are also discussed.

Wagner, Paul K.↗
NASA NTRS1991

Combinatorial FSK modulation for power-efficient high-rate communications

Deep-space and satellite communications systems must be capable of conveying high-rate data accurately with low transmitter power, often through dispersive channels. A class of noncoherent Combinatorial Frequency Shift Keying (CFSK) modulation schemes is investigated which address these needs. The bit error rate performance of this class of modulation formats is analyzed and compared to the more traditional modulation types. Candidate modulator, demodulator, and digital signal processing (DSP) hardware structures are examined in detail. System-level issues are also discussed.

Wagner, Paul K.↗
NASA NTRS1990

Lightweight concentrator module with 30 percent AM0 efficient GaAs/GaSb tandem cells

A concept is presented for an aerospace concentrator module with lightweight domed lenses and 30 percent AM0 efficient GaAs/GaSb tandem solar cell circuits. The performance of transparent GaAs cells is reviewed. NASA's high-altitude jet flight calibration data for recent GaSb cells assembled with bulk GaAs filters are reported, along with subsequent Boeing and NASA measurements of GaSb I-V performance at various light levels and temperatures. The expected performance of a basic two-terminal tandem concentrator circuit with three-to-one voltage matching is discussed. All of the necessary components being developed to assemble complete flight test coupons are shown. Straightforward interconnect and assembly techniques yield voltage matched circuits with near-optimum performance over a wide temperature range.

Avery, J. E.↗
NASA NTRS1986

Active Q switching in a GaAs/AlGaAs multiquantum well laser with an intracavity monolithic loss modulator

Active Q switching in a GaAs/AlGaAs multiquantum well laser with an intracavity electroabsorption monolithic loss modulator is demonstrated. In this device, an efficient loss modulation is achieved through the quantum confined Stark effect in a modulator section and the enhanced carrier induced band shrinkage effect in an optical amplifier section. It is found that a picosecond pulse as narrow as 18.6 ps full width at half-maximum is generated and a high repetition rate of more than 3 GHz is obtained.

Arakawa, Y.↗
NASA NTRS1987

Bandwidth efficient block codes for M-ary PSK modulation

A class of bandwidth efficient block codes for M-ary PSK modulation is presented. A soft-decision decoding for this class of codes is devised. Some specific short codes for Quad Phase Shift Key (QPSK), 8-PSK and 16-PSK modulations are constructed. These codes have good minimum squared Euclidean distances and provide 2 to 5.8 dB coding gains over uncoded QPSK modulation without (or with little) bandwidth expansion. The complete weight distributions of these specific codes are determined. Based on these weight distributions, their error probabilities are evaluated. Some of these codes have simple trellis structures and hence can be decoded by Viterbi decoding algorithm with relatively simple implementation. Moreover, the codes are very suitable for use as inner codes for various cascaded coding schemes with Reed-Solomon codes as outer codes.

Lin, Shu↗
NASA NTRS1977

High efficiency, long life terrestrial solar panel

The design of a high efficiency, long life terrestrial module was completed. It utilized 256 rectangular, high efficiency solar cells to achieve high packing density and electrical output. Tooling for the fabrication of solar cells was in house and evaluation of the cell performance was begun. Based on the power output analysis, the goal of a 13% efficiency module was achievable.

Chao, T.↗
NASA NTRS2016

The Description and Validation of a Computationally-Efficient CH4-CO-OH (ECCOHv1.01) Chemistry Module for 3D Model Applications

We present the Efficient CH4-CO-OH (ECCOH) chemistry module that allows for the simulation of the methane, carbon monoxide, and hydroxyl radical (CH4-CO- OH) system, within a chemistry climate model, carbon cycle model, or Earth system model. The computational efficiency of the module allows many multi-decadal sensitivity simulations of the CH4-CO-OH system, which primarily determines the global atmospheric oxidizing capacity. This capability is important for capturing the nonlinear feedbacks of the CH4-CO-OH system and understanding the perturbations to methane, CO, and OH, and the concomitant impacts on climate. We implemented the ECCOH chemistry module in the NASA GEOS-5 atmospheric global circulation model (AGCM), performed multiple sensitivity simulations of the CH4-CO-OH system over 2 decades, and evaluated the model output with surface and satellite data sets of methane and CO. The favorable comparison of output from the ECCOH chemistry module (as configured in the GEOS- 5 AGCM) with observations demonstrates the fidelity of the module for use in scientific research.

carbon cycle model↗
NASA NTRS1987

Assessment Of Advanced Concentrator Photovoltaic Modules

Computer program developed to estimate probabilistically total and component costs to end users of concentrating photovoltaic arrays in 1990's. Based on modified version of SIMRAND program, Simulation of Research and Development projects, -to estimate total cost of system for large number of module designs. Module design that yields minimum cost for total system then chosen as preferred design. To obtain distribution of expected module costs, simulation performed. Component estimates made by SIMRAND include efficiency of module and costs of cell, assembly of cells, lenses, and modules. Written in FORTRAN 77.

Borden, C. S.↗
NASA NTRS1988

Orbital Maneuvering Vehicle (OMV) remote servicing kit

With the design and development of the Orbital Maneuvering Vehicle (OMV) progressing toward an early 1990 initial operating capability (IOC), a new era in remote space operations will evolve. The logical progression to OMV front end kits would make available in situ satellite servicing, repair, and consummables resupply to the satellite community. Several conceptual design study efforts are defining representative kits (propellant tanks, debris recovery, module servicers); additional focus must also be placed on an efficient combination module servicer and consummables resupply kit. A remote servicer kit of this type would be designed to perform many of the early maintenance/resupply tasks in both nominal and high inclination orbits. The kit would have the capability to exchange Orbital Replacement Units (ORUs), exchange propellant tanks, and/or connect fluid transfer umbilicals. Necessary transportation system functions/support could be provided by interfaces with the OMV, Shuttle (STS), or Expendable Launch Vehicle (ELV). Specific remote servicer kit designs, as well as ground and flight demonstrations of servicer technology are necessary to prepare for the potential overwhelming need. Ground test plans should adhere to the component/system/breadboard test philosophy to assure maximum capability of one-g testing. The flight demonstration(s) would most likely be a short duration, Shuttle-bay experiment to validate servicer components requiring a micro-g environment.

Brown, Norman S.↗
NASA NTRS1987

Performance improvements in silicon flat-plate cells and modules

This paper reports the development of a flat-plate module based on highly efficient ion-implanted silicon solar cells. The cells developed in this work are 53 sq cm in area and have exhibited AM 1.5 efficiencies of over 18 percent. The use of back surface reflectors to reduce module operating temperature is discussed. A comparison of various approaches to cell design is made, and module test data for these designs are presented. A comparison of float zone and Czochralski silicon is made. Module efficiency of over 15 percent (at 25 C) is reported.

Spitzer, M. B.↗