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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

A production parylene coating process for hybrid microcircuits

The real impetus for developing a production parylene coating process for internal hybrid passivation came as a result of the possibility of loose conductive particles in hybrid microelectronic circuits, causing intermittent and sometimes permanent failures. Because of the excellent mechanical properties of parylene, it is capable of securing the loose particles in place and prevent such failures. The process of coating described consists of (1) vaporizing the initial charge, which is in the form of a dimer; (2) conversion of the dimer into a reactive monomer; and (3) deposition and subsequent polymerization of the monomer in the deposition chamber which forms a uniform parylene film over all the cold surfaces in contact. Experimental results are discussed in terms of wire bond reliability, resistor drift, high-temperature storage characteristics of parylene, and coating acceptance standards. It is concluded that internal cavities of microelectronic circuits can be successfully coated with parylene provided appropriate tooling is used to protect external leads from the parylene monomer.

Kale, V. S.↗
NASA NTRS1979

Eliminating gold migration in microcircuits

Report discusses how effects of moisture and other factors causing bridging between conductors can be prevented. Study details how several factors such as contaminants, large packages, high voltage, narrow conductor spacing and temperature contribute to moisture problems.

Dermarderosian, A.↗
NASA NTRS1977

Optical scanning tests of complex CMOS microcircuits

The new test method was based on the use of a raster-scanned optical stimulus in combination with special electrical test procedures. The raster-scanned optical stimulus was provided by an optical spot scanner, an instrument that combines a scanning optical microscope with electronic instrumentation to process and display the electric photoresponse signal induced in a device that is being tested.

Levy, M. E.↗
NASA NTRS1977

A hermetic sealing process for large irregularly shaped hybrid microcircuit enclosures

A system for sealing vacuum baked hybrids in a dry inert atmosphere using an overlapping spot resistance weld is described. A unique electrode configuration and fixturing that permits sealing of large and irregularly shaped gold plated Kovar packages to the hermeticity requirements of MIL-STD-883 was discussed. Metallurgical considerations and comparisons to laser sealing were made. Problems encountered during the development and optimization of the process were highlighted. Solutions to plating, fixturing, warpage, weld splatter and cracked bead problems are presented.

Stahler, M. R.↗
NASA NTRS1977

Reliability evaluation of hermetic dual in-line flat microcircuit packages

The relative strengths and weaknesses of 35 commonly used hermetic flat and dual in-line packages were determined and used to rank each of the packages according to a numerical weighting scheme for package attributes. The list of attributes included desirable features in five major areas: lead and lead seal, body construction, body materials, lid and lid seal, and marking. The metal flat pack and multilayer integral ceramic flat pack and DIP received the highest rankings, and the soft glass Cerdip and Cerpak types received the lowest rankings. Loss of package hermeticity due to lead and lid seal problems was found to be the predominant failure mode from the literature/data search. However, environmental test results showed that lead and lid seal failures due to thermal stressing was only a problem with the hard glass (Ceramic) body DIP utilizing a metal lid and/or bottom. Insufficient failure data were generated for the other package types tested to correlate test results with the package ranking.

Johnson, G. M.↗
NASA NTRS1979

Electrical Characterization of Hughes HCMP 1853D and RCA CDP1853D N-bit, CMOS, 1-of-8 Decoder Microcircuits

Electrical characterization tests were performed on two different manufactured types of integrated circuits. The devices were subjected to functional and AC and DC parametric tests at ambient temperatures of -55 C, -20 C, 25 C, 85 C, and 125 C. The data were analyzed and tabulated to show the effect of operating conditions on performance and to indicate parameter deviations among devices in each group. Accuracy was given precedence over test time efficiency where practical, and tests were designed to measure worst case performance.

Stokes, R. L.↗
NASA NTRS1980

Coatings for hybrid microcircuits

Silicone or parylene coatings protect circuits from damage by battery of military standard tests. PIND (Partical Impact Noise Detection) test proved unreliable in predicting failure for either coated or uncoated circuits.

Kinser, D. L.↗
NASA NTRS1976

Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

Mandal, R. P.↗
NASA NTRS1983

Low-Cost Alternatives in Hybrid Microcircuit Packaging

Adhesive sealing, nickel plating, and multiwire boards evaluated. Based on study involving fully developed hardware, report considers adhesive packaging instead of seam welding, nickel-plated Kovar (commercial Fe/NI/Co alloy) packages instead of gold plates ones, and multiwire circuit boards instead of multilayer boards as alternatives for reducing cost of hardware without reducing reliability.

Caruso, S. V.↗
NASA NTRS1981

Development of low cost custom hybrid microcircuit technology

Selected potentially low cost, alternate packaging and interconnection techniques were developed and implemented in the manufacture of specific NASA/MSFC hardware, and the actual cost savings achieved by their use. The hardware chosen as the test bed for this evaluation ws the hybrids and modules manufactured by Rockwell International fo the MSFC Flight Accelerometer Safety Cut-Off System (FASCOS). Three potentially low cost packaging and interconnection alternates were selected for evaluation. This study was performed in three phases: hardware fabrication and testing, cost comparison, and reliability evaluation.

Perkins, K. L.↗
NASA NTRS1985

Accelerators for critical experiments involving single-particle upset in solid-state microcircuits

Charged-particle interactions in microelectronic circuit chips (integrated circuits) present a particularly insidious problem for solid-state electronic systems due to the generation of soft errors or single-particle event upset (SEU) by either cosmic rays or other radiation sources. Particle accelerators are used to provide both light and heavy ions in order to assess the propensity of integrated circuit chips for SEU. Critical aspects of this assessment involve the ability to analytically model SEU for the prediction of error rates in known radiation environments. In order to accurately model SEU, the measurement and prediction of energy deposition in the form of an electron-hole plasma generated along an ion track is of paramount importance. This requires the use of accelerators which allow for ease in both energy control (change of energy) and change of ion species. This and other aspects of ion-beam control and diagnostics (e.g., uniformity and flux) are of critical concern for the experimental verification of theoretical SEU models.

Zoutendyk, J. A.↗
NASA NTRS1986

Method of examining microcircuit patterns

Examination of microstructures of LSI and VLSI devices is facilitated by employing a method in which the device is photographed through a darkfield illumination optical microscope and the resulting negative subjected to inverse processing to form a positive on a photographic film. The film is then developed to form photographic prints or transparencies which clearly illustrate the structure of the device. The entire structure of a device may be examined by alternately photographing the device and selectively etching layers of the device in order to expose underlying layers.

Suszko, S. F.↗
NASA NTRS1986

Applications of heat pipes to cool PWBS and hybrid microcircuits

Some of the advanced thermal management techniques used to reduce operating junction temperature under extreme environmental temperature conditions are discussed. Heat pipes in actual electronic packaging applications, and those under development, are discussed. Performance characteristics of heat pipes are given, and examples are described of how thermal problems in electronic packaging are solved through the use of heat pipes.

Sekhon, K. S.↗
NASA NTRS1987

CMOS detector cells for holographic optical interconnects in microcircuits

This paper reports on the characterization of CMOS detectors for holographic optical interconnects in micro circuits. A VLSI temporal response system has been built, which has high-magnification viewing capabilities to facilitate the identification of the sample area under investigation. An isolated photodiode and load circuit has been characterized to determine responsivity, response time, and light spot positioning effects. The threshold of optical gate cells incorporating the above detectors and a transistor inverter stage to couple to other circuitry has been determined. The rise time and fall time of the optical gate cells have also been determined experimentally. The results were compared with the results of SPICE simulation, and show satisfactory agreement. The time delay of optical gate cell output was thus determined to be 70 ns at 10 microW light input. Threshold power was 0.5 microW light input.

Wu, W. H.↗
NASA NTRS1989

Effects of space radiation on electronic microcircuits

The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.

Kolasinski, W. A.↗
NASA NTRS2008

Failures in Hybrid Microcircuits During Environmental Testing. History Cases

This purpose of this viewgraph presentation is to discuss failures in hermetic hybrids observed at the GSFC PA Lab during environmental stress testing. The cases discussed are: Case I. Substrate metallization failures during Thermal cycling (TC). Case II. Flex lid-induced failure. Case Ill. Hermeticity failures during TC. Case IV. Die metallization cracking during TC. and how many test cycles and parts is necessary? Case V. Wire Bond failures after life test. Case VI. Failures caused by Au/In IMC growth.

Teverovsky, Alexander↗