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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Memory forensic analysis of a programmable logic controller in industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLCs) are used to automate physical processes such as nuclear plants and power grid stations, and are often subject to cyber attacks. As in conventional IT domain, the memory analysis of the PLCs can help answer important forensic questions about the attack, such as the presence of malicious firmware, injection of modified control logic (the program running on the PLC), and manipulation of I/O devices (e.g., sensors and actuators). Unlike conventional IT domain, PLCs have heterogeneous hardware architecture, proprietary firmware and control software, making it challenging to employ a unified framework for their memory forensics. For merely extracting artifacts of forensic importance, reverse-engineering the firmware is a tedious task, and the effort needs to be repeated for every PLC model. As a community, a step-wise approach to tackle this challenge is to analyze the memory of specific PLCs, and subsequently find a generic framework applicable to all PLCs. Our work is a step forward in this direction. By following a methodology that focuses on the functional layer of PLCs instead of reverse engineering the firmware, we analyze the digital forensic artifacts available in a common PLC, Allen-Bradley ControlLogix 1756-L61. Before diving into the memory dump, we analyze the PLC control software to create a list of important artifacts that are sure to exist in the PLC memory dump. The approach employs a setup where PLC control software RSLogix-5000 is connected to the PLC, and the memory dump can be obtained as and when needed. We create test cases that sequentially highlight each category of artifacts, followed by an examination of the resultant impact on memory. After attaining the listed artifacts, we employ conventional string and known data searches to extract interesting information present in this PLC's memory. The memory analysis profile, presented as a Python library and shared with the community, can help a forensic investigator to readily extract forensic artifacts from the same model's controller. The adopted approach may help researchers in creating memory profile of other PLCs, and ultimately formulating a generic PLC memory analysis framework.

Rais, Muhammad Haris↗
DOE OSTI2020

Fractionation of Lignin for Selective Shape Memory Effects at Elevated Temperatures

We report a facile approach to control the shape memory effects and thermomechanical characteristics of a lignin-based multiphase polymer. Solvent fractionation of a syringylpropane-rich technical organosolv lignin resulted in selective lignin structures having excellent thermal stability coupled with high stiffness and melt-flow resistance. The fractionated lignins were reacted with rubber in melt-phase to form partially networked elastomer enabling selective programmability of the material shape either at 70 °C, a temperature that is high enough for rubbery matrix materials, or at an extremely high temperature, 150 °C. Utilizing appropriate functionalities in fractionated lignins, tunable shape fixity with high strain and stress recovery, particularly high-stress tolerance were maintained. Detailed studies of lignin structures and chemistries were correlated to molecular rigidity, morphology, and stress relaxation, as well as shape memory effects of the materials. The fractionation of lignin enabled enrichment of specific lignin properties for efficient shape memory effects that broaden the materials’ application window. Electron microscopy, melt-rheology, dynamic mechanical analysis and ultra-small angle neutron scattering were conducted to establish morphology of acrylonitrile butadiene rubber (NBR)-lignin elastomers from solvent fractionated lignins.

36 MATERIALS SCIENCE↗
NASA NTRS2008

Ring Bus Architecture for a Solid-State Recorder

A document concisely describes a ring bus architecture for a proposed solid-state recorder (SSR) that would serve as buffer of data to be transmitted from a spacecraft to Earth. This architecture would afford fault tolerance needed for reliable operation in an anticipated high-radiation environment in which traditional SSRs cannot operate reliably. Features of the architecture include one or more controller boards and multiple memory boards interconnected in a ringlike topology. The interconnections would be high-speed serial links complying with the Institute of Electrical and Electronics Engineers (IEEE) standard 1393 (which pertains to a spaceborne fiber-optic data bus). Accordingly, each controller and memory board would be equipped with an IEEE-1393-compliant ring-bus-interface unit. The ringlike topology and the multiplicity of memory boards (and, optionally, of controller boards) would afford the redundancy needed for fault tolerance. Each board would be a fault-containment region. The IEEE 1393 links could be routed so that the SSR would continue to function even in the event of multiple failures. This architecture would also support scalability over a wide range. In a fully redundant configuration, it could accommodate between 1 and 125 memory boards.

Walker, W. John↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS1980

A bubble memory module

A bubble memory module design providing flexibility for many user applications in spacecraft data recording is described. The memory module can be used with user-designed controllers with the memory organization determined by the application. Asynchronous data rates from zero to 1.33 Mbits/sec at minimum power are accomplished by using 8-chip memory cells with 100 K bit serial chips. The memory module is expandable from a 4 x 2 cell matrix to a 4 x 16 cell matrix corresponding to an expandable capacity of 6.55 M to 52.4 M bits. The module's design, utility in various memory systems, and user clocking scheme are described.

Hayes, P. J.↗
NASA NTRS2004

Design and Control of a Proof-of-Concept Active Jet Engine Intake Using Shape Memory Alloy Actuators

The design and control of a novel proof-of-concept active jet engine intake using Nickel-Titanium (Ni-Ti or Nitinol) shape memory alloy (SMA) wire actuators is used to demonstrate the potential of an adaptive intake to improve the fuel efficiency of a jet engine. The Nitinol SMA material is selected for this research due to the material's ability to generate large strains of up to 5 percent for repeated operations, a high power-to-weight ratio, electrical resistive actuation, and easy fabrication into a variety of shapes. The proof-of-concept engine intake employs an overlapping leaf design arranged in a concentric configuration. Each leaf is mounted on a supporting bar that rotates upon actuation by SMA wires electrical resistive heating. Feedback control is enabled through the use of a laser range sensor to detect the movement of a leaf and determine the radius of the intake area. Due to the hysteresis behavior inherent in SMAs, a nonlinear robust controller is used to direct the SMA wire actuation. The controller design utilizes the sliding-mode approach to compensate for the nonlinearities associated with the SMA actuator. Feedback control experiments conducted on a fabricated proof-of-concept model have demonstrated the capability to precisely control the intake area and achieve up to a 25 percent reduction in intake area. The experiments demonstrate the feasibility of engine intake area control using the proposed design.

Song, Gangbing↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2021

Nonvolatile Voltage Controlled Molecular Spin-State Switching for Memory Applications

Nonvolatile, molecular multiferroic devices have now been demonstrated, but it is worth giving some consideration to the issue of whether such devices could be a competitive alternative for solid-state nonvolatile memory. For the Fe (II) spin crossover complex [Fe{H2B(pz)2}2(bipy)], where pz = tris(pyrazol-1-yl)-borohydride and bipy = 2,2′-bipyridine, voltage-controlled isothermal changes in the electronic structure and spin state have been demonstrated and are accompanied by changes in conductance. Higher conductance is seen with [Fe{H2B(pz)2}2(bipy)] in the high spin state, while lower conductance occurs for the low spin state. Plausibly, there is the potential here for low-cost molecular solid-state memory because the essential molecular thin films are easily fabricated. However, successful device fabrication does not mean a device that has a practical value. Here, we discuss the progress and challenges yet facing the fabrication of molecular multiferroic devices, which could be considered competitive to silicon.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1996

Shape Control of Solar Collectors Using Shape Memory Alloy Actuators

Solar collectors that are focused on a central receiver are designed with a mechanism for defocusing the collector or disabling it by turning it out of the path of the sun's rays. This is required to avoid damaging the receiver during periods of inoperability. In either of these two cases a fail-safe operation is very desirable where during power outages the collector passively goes to its defocused or deactivated state. This paper is principally concerned with focusing and defocusing the collector in a fail-safe manner using shape memory alloy actuators. Shape memory alloys are well suited to this application in that once calibrated the actuators can be operated in an on/off mode using a minimal amount of electric power. Also, in contrast to other smart materials that were investigated for this application, shape memory alloys are capable of providing enough stroke at the appropriate force levels to focus the collector. Design and analysis details presented, along with comparisons to test data taken from an actual prototype, demonstrate that the collector can be repeatedly focused and defocused within accuracies required by typical solar energy systems. In this paper the design, analysis and testing of a solar collector which is deformed into its desired shape by shape memory alloy actuators is presented. Computations indicate collector shapes much closer to spherical and with smaller focal lengths can be achieved by moving the actuators inward to a radius of approximately 6 inches. This would require actuators with considerably more stroke and some alternate SMA actuators are currently under consideration. Whatever SMA actuator is finally chosen for this application, repeatability and fatigue tests will be required to investigate the long term performance of the actuator.

Lobitz, D. W.↗
NASA NTRS1969

Circuitry selectively limits data storage in general purpose computer

Circuitry limits storage in the memory of a stored program general purpose digital computer by permitting storage or writing to certain, specified areas of memory. The limit register used in the computer is easily set under program control, and the memory block size and position is readily changed to suit each specific program.

Slopper, D. K.↗
NASA NTRS2010

Flash drive memory apparatus and method

A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

Hinchey, Michael G.↗
NASA NTRS2018

Radiation Performance of Memory Technologies for Space Applications

MRAM and DRAM memory technologies identified for possible radiation hardening were investigated for memory-array- and controller-level radiation sensitivity. TID and SEE performance of memory arrays and associated cells is good, but with some questions about viability of hardening of problematic control circuitry. Control-circuitry-related SEE problems are highlighted. TID data are focused on memory arrays only.

Some, Raphael↗
DOE OSTI2025

Fast Sideband Control of a Weakly Coupled Multimode Bosonic Memory

Circuit quantum electrodynamics (cQED) with superconducting cavities coupled to nonlinear circuits like transmons offers a promising platform for hardware-efficient quantum information processing. We address critical challenges in realizing this architecture by weakening the dispersive coupling while also demonstrating fast, high-fidelity multimode control by dynamically amplifying gate speeds through transmon-mediated sideband interactions. This approach enables transmon-cavity SWAP gates, for which we achieve speeds up to 30 times larger than the bare dispersive coupling. Combined with transmon rotations, this allows for efficient, universal state preparation in a single cavity mode, though achieving unitary gates and extending control to multiple modes remains a challenge. In this work, we overcome this by introducing two sideband control strategies: (1) a shelving technique that prevents unwanted transitions by temporarily storing populations in sideband-transparent transmon states and (2) a method that exploits the dispersive shift to synchronize sideband transition rates across chosen photon-number pairs to implement transmon-cavity SWAP gates that are selective on photon number. We leverage these protocols to prepare Fock and binomial code states across any of ten modes of a multimode cavity with millisecond cavity coherence times. We demonstrate the encoding of a qubit from a transmon into arbitrary vacuum and Fock state superpositions, as well as entangled NOON states of cavity mode pairs— a scheme extendable to arbitrary multimode Fock encodings. Furthermore, we implement a new binomial encoding gate that converts arbitrary transmon superpositions into binomial code states in $\qty{4}{\micro\second}$ (less than $1/\chi$), achieving an average post-selected final state fidelity of $\qty{96.3}{\percent}$ across different fiducial input states.

Huang, Jordan [Rutgers U., Piscataway]↗
NASA NTRS2005

Finite Element Analysis of Adaptive-Stiffening and Shape-Control SMA Hybrid Composites

Shape memory alloy hybrid composites with adaptive-stiffening or morphing functions are simulated using finite element analysis. The composite structure is a laminated fiber-polymer composite beam with embedded SMA ribbons at various positions with respect to the neutral axis of the beam. Adaptive stiffening or morphing is activated via selective resistance heating of the SMA ribbons or uniform thermal loads on the beam. The thermomechanical behavior of these composites was simulated in ABAQUS using user-defined SMA elements. The examples demonstrate the usefulness of the methods for the design and simulation of SMA hybrid composites. Keywords: shape memory alloys, Nitinol, ABAQUS, finite element analysis, post-buckling control, shape control, deflection control, adaptive stiffening, morphing, constitutive modeling, user element

Gao, Xiujie↗
NASA NTRS1993

Distributed simulation using a real-time shared memory network

The Advanced Control Technology Branch of the NASA Lewis Research Center performs research in the area of advanced digital controls for aeronautic and space propulsion systems. This work requires the real-time implementation of both control software and complex dynamical models of the propulsion system. We are implementing these systems in a distributed, multi-vendor computer environment. Therefore, a need exists for real-time communication and synchronization between the distributed multi-vendor computers. A shared memory network is a potential solution which offers several advantages over other real-time communication approaches. A candidate shared memory network was tested for basic performance. The shared memory network was then used to implement a distributed simulation of a ramjet engine. The accuracy and execution time of the distributed simulation was measured and compared to the performance of the non-partitioned simulation. The ease of partitioning the simulation, the minimal time required to develop for communication between the processors and the resulting execution time all indicate that the shared memory network is a real-time communication technique worthy of serious consideration.

Simon, Donald L.↗