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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Monitor/alarm with audio and visual warning output can be used to warn when prescribed limits of temperature, liquid level, pressure, or similar properties are exceeded. Device is more compact, lighter, and less expensive to manufacture than typical alarm circuits.
Ceramic capacitors failed insulation resistance testing at less than one-tenth their rated voltage. Many failures recovered as the voltage was increased. Comprehensive failure analysis techniques, some of which are unprecedented, were used to examine these failures. It was determined that there was more than one failure mechanism, and the results indicate a need for special additional screening.
Short-circuit current provides minimum memory power. Protective circuit includes dc-to-dc converter that supplies keep-alive voltage to memories when short circuit occurs in any of system loads. Converter powered by lowvoltage across two of three series diodes generated by short-circuit bus current. Relay switch is in open (short-circuit-detected) position. Protective circuit useful wherever necessary to improve reliability of volatile memories or other circuits that must not lose power.
This thesis addresses the acoustoelectric issues concerning the amplification of surface acoustic waves (SAWs) and the reflection of SAWs from slanted reflector gratings on GaAs, with application to a novel acoustic charge transport (ACT) device architecture. First a simple model of the SAWAMP was developed, which was subsequently used to define the epitaxially grown material structure necessary to provide simultaneously high resistance and high electron mobility. In addition, a segmented SAWAMP structure was explored with line widths on the order of an acoustic wavelength. This resulted in the demonstration of SAWAMPS with an order of magnitude less voltage and power requirements than previously reported devices. A two-dimensional model was developed to explain the performance of devices with charge confinement layers less then 0.5 mm, which was experimentally verified. This model was extended to predict a greatly increased gain from the addition of a ZnO overlay. These overlays were experimentally attempted, but no working devices were reported due to process incompatibilities. In addition to the SAWAMP research, the reflection of SAWs from slanted gratings on GaAs was also studied and experimentally determined reflection coefficients for both 45 deg grooves and Al stripes on GaAs have been reported for the first time. The SAWAMp and reflector gratings were combined to investigate the integrated ring oscillator for application to the proposed ACT device and design parameters for this device have been provided.
This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV; and a rail-to-rail, constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35~1 partially-depleted Silicon-on-Insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.
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Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.
Introduction of BME capacitors to high-reliability electronics as a replacement for PME capacitors requires better understanding of changes in performance and reliability of MLCCs to set justified screening and qualification requirements. In this work, absorption and leakage currents in various lots of commercial and military grade X7R MLCCs rated to 100V and less have been measured to reveal difference in behavior of PME and BME capacitors in a wide range of voltages and temperatures. Degradation of leakage currents and failures in virgin capacitors and capacitors with introduced cracks has been studied at different voltages and temperatures during step stress highly accelerated life testing. Mechanisms of charge absorption, conduction and degradation have been discussed and a failure model in capacitors with defects suggested.
Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.
Reliability of base metal electrode (BME) multilayer ceramic capacitors (MLCCs) that until recently were used mostly in commercial applications, have been improved substantially by using new materials and processes. Currently, the inception of intrinsic wear-out failures in high quality capacitors became much greater than the mission duration in most high-reliability applications. However, in capacitors with defects degradation processes might accelerate substantially and cause infant mortality failures. In this work, a physical model that relates the presence of defects to reduction of breakdown voltages and decreasing times to failure has been suggested. The effect of the defect size has been analyzed using a thermal runaway model of failures. Adequacy of highly accelerated life testing (HALT) to predict reliability at normal operating conditions and limitations of voltage acceleration are considered. The applicability of the model to BME capacitors with cracks is discussed and validated experimentally.
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A compact particle accelerator can include two or more cavities disposed along an axis of the particle accelerator, each of which is coupled to two or more drivers. The accelerator can also include a power supply coupled to the two or more drivers such that a particle beam traveling along the axis is accelerated. The power supply can be an interface with a commercial power outlet, battery power, or a combination thereof depending upon the use case. Example configurations of the accelerator include hand held or mobile devices that are capable of delivering up to and greater than a 1 MeV electron beam.
A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.
A compact particle accelerator can include two or more cavities disposed along an axis of the particle accelerator, each of which is coupled to two or more drivers. The accelerator can also include a power supply coupled to the two or more drivers such that a particle beam traveling along the axis is accelerated. The power supply can be an interface with a commercial power outlet, battery power, or a combination thereof depending upon the use case. Example configurations of the accelerator include hand held or mobile devices that are capable of delivering up to and greater than a 1 MeV electron beam.
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Abstract not provided.
Shockley-Read-Hall (SRH) generation and/or recombination in heterojunction devices is suppressed by unconventional doping at or near the heterointerface. The effect of this doping is to shift SRH generation and/or recombination preferentially into the wider band gap material of the heterojunction. This reduces total SRH generation and/or recombination in the device by decreasing the intrinsic carrier concentration ni at locations where most of the SRH generation and/or recombination occurs. The physical basis for this effect is that the SRH generation and/or recombination rate tends to decrease as ni around the depletion region decreases, so decreasing the effective ni in this manner is a way to decrease SRH recombination.
The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.