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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.
A semiconductor optical integrated circuit for wave division multiplexing has a semiconductor waveguide layer, a succession of diffraction grating points in the waveguide layer along a predetermined diffraction grating contour, a semiconductor diode array in the waveguide layer having plural optical ports facing the succession of diffraction grating points along a first direction, respective semiconductor diodes in the array corresponding to respective ones of a predetermined succession of wavelengths, an optical fiber having one end thereof terminated at the waveguide layer, the one end of the optical fiber facing the succession of diffraction grating points along a second direction, wherein the diffraction grating points are spatially distributed along the predetermined contour in such a manner that the succession of diffraction grating points diffracts light of respective ones of the succession of wavelengths between the one end of the optical fiber and corresponding ones of the optical ports.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.
Computer oriented modeling of integrated circuits - algorithms for dichotomous presentation of active networks
New technologies like Smart Power, and Power Integrated Circuits are the wave of the future in providing high performance low cost power conditioning subsystem (PCS)in small to large power applications. This paper discusses circuit designs using these devices that are suitable for PCS in photovoltaic and other industrial applications such as electrical appliances, instrumentation, AC motor drives, battery chargers, automobiles, telecommunications, UPS, and switch mode power supplies. It examines the cost of high volume production and current technological barriers asociated with the development of these technologies.
The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.
Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.
The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.
Development of packaging system for mounting beam lead integrated chip circuit on lead frame is discussed. Process for fabricating large scale integration circuits is described. Diagrams illustrating method of construction are included.
Integrated circuit control and timing system of high altitude rocket radar
Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.
Distribution plots of electrical parameters as means of investigating potential reliability of integrated circuits
Resistance multiplication in RC integrated circuit design by switching
Refractory dielectric for integrated circuits
Refractory material dielectrics for integrated circuits
Holographic microscopy technique fundamentals and electrically activated integrated circuit changes inspection