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At least 127 records · Page 7

10 Gigabit Ethernet Performance on SGI Altix and Origin Systems

As the state of high performance computing continues to advance, the size of datasets continue to grow, driving a need for high bandwidth data networks. family of networks. 10 Gigabit Ethernet is the latest step in the popular Ethernet We have evaluated the S2io Xframe 10 Gigabit Ethernet adapter on 512p SGI Altix systems running ProPack 3, and Origin systems running Irix 6.5.24 and 6.5.26 in our production supercomputing environment. We encountered a number of performance and stability issues, which were promptly dealt with by SGI and S2io. Using nttcp we tested TCP performance for single and multiple streams, and we tested file transfer using NFS and bbftp. We will present the results of our testing, including the effects of various tuning options on throughput and CPU utilization, and offer suggestions for configuring and tuning S2io 10 Gigabit Ethernet cards in an Altix/Linux or Origin/Irix environment.

Meyer, Andy↗

Standardizing Microprocessor and GPU Radiation Test Approaches

Microprocessor, Graphics Processing Units (GPUs) and DDRx memory devices have emerged as promising next-generation technologies that enables both high performance processing and acceleration of complex algorithms for the latest challenges in human spaceflight, autonomous vehicles and artificial intelligence (AI). The feature sets of these devices offer exponential increases to throughput, calculation capability and system autonomy when compared to legacy flight systems. NASA's Electronic Part and Packaging (NEPP) Program has conducted an investigation into the radiation susceptibility of leading edge devices and process technologies by establishing standardized test approaches. Unlike most discrete devices, these require state of the art test systems to induce specific hardware activity similar to application software, thus allowing the characterization of failure modes within the system. To best characterize the tested part, NEPP eliminates variables that may impact device performance under radiation. Simplification of remaining system-level variables leads to an improved understanding of complex computational devices and their intended applications. The failure modes and error signatures that are recorded during testing are used to determine radiation sensitivity of the semiconductor process and the microcode architecture of the design. This presentation will discuss the test methodology that NASA Electronic Parts and Packaging (NEPP) is working to establish for its microprocessor, GPU and DDRx memory test programs to provide guidance on these devices and their underlying technology, in regards to their potential usage in future space flight systems.

GPU↗

Assessments of Hollow Cathode Wear in the Xenon Ion Propulsion System (XIPs(c)) by Numerical Analyses and Wear Tests

The standard approach presently followed by NASA to qualify electric propulsion for the required mission throughput has been based largely on life tests, which can be costly and time consuming. Revised electric propulsion lifequalification approaches are being formulated that combine analytical and/or computational methods with (shorter-duration) wear tests. As a model case, a wear test is being performed at JPL to assess the lifetime of the discharge hollow cathode in the Xenon Ion Propulsion System (XIPS(c)), a 25-cm ion engine developed by L-3 Communications Electron Technologies, Inc. for commercial applications. Wear and plasma data accumulated throughout this life-assessment program are being used to validate the existing 2-D hollow cathode code OrCa2D. We find that the OrCa2D steady-state solution predicts very well the time-averaged plasma data and the keeper voltage after 5500 hrs of operation in high-power mode. When the wave motion that occurs naturally in these devices is accounted for, based on an estimate of the maximum wave amplitude, the molybdenum-keeper erosion profile observed in the XIPS(c) discharge cathode is also reproduced within a factor of two of the observation. When the same model is applied to predict the erosion of a tantalum keeper we find that erosion is reduced by more than two orders of magnitude compared to the molybdenum keeper due the significantly lower sputtering yield of tantalum. A tantalum keeper would therefore allow keeper lifetimes that greatly exceed the present requirements for deep-space robotic missions considered by NASA. Moreover, such large reduction of the erosion renders the largest uncertainties in the models, which are associated with the wave amplitude estimates and the electron transport model, negligible.

plasma simulations↗

Fault-Tolerant Software-Defined Radio on Manycore

Software-defined radio (SDR) platforms generally rely on field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), but such architectures require significant software development. In addition, application demands for radiation mitigation and fault tolerance exacerbate programming challenges. MaXentric Technologies, LLC, has developed a manycore-based SDR technology that provides 100 times the throughput of conventional radiationhardened general purpose processors. Manycore systems (30-100 cores and beyond) have the potential to provide high processing performance at error rates that are equivalent to current space-deployed uniprocessor systems. MaXentric's innovation is a highly flexible radio, providing over-the-air reconfiguration; adaptability; and uninterrupted, real-time, multimode operation. The technology is also compliant with NASA's Space Telecommunications Radio System (STRS) architecture. In addition to its many uses within NASA communications, the SDR can also serve as a highly programmable research-stage prototyping device for new waveforms and other communications technologies. It can also support noncommunication codes on its multicore processor, collocated with the communications workload-reducing the size, weight, and power of the overall system by aggregating processing jobs to a single board computer.

Ricketts, Scott↗

Rapid Chemometric Filtering of Spectral Data

A method of rapid, programmable filtering of spectral transmittance, reflectance, or fluorescence data to measure the concentrations of chemical species has been proposed. By programmable is meant that a variety of spectral analyses can readily be performed and modified in software, firmware, and/or electronic hardware, without need to change optical filters or other optical hardware of the associated spectrometers. The method is intended to enable real-time identification of single or multiple target chemical species in applications that involve high-throughput screening of multiple samples. Examples of such applications include (but are not limited to) combinatorial chemistry, flow cytometry, bead assays, testing drugs, remote sensing, and identification of targets. The basic concept of the proposed method is to perform real-time crosscorrelations of a measured spectrum with one or more analytical function(s) of wavelength that could be, for example, the known spectra of target species. Assuming that measured spectral intensities are proportional to concentrations of target species plus background spectral intensities, then after subtraction of background levels, it should be possible to determine target species concentrations from cross-correlation values. Of course, the problem of determining the concentrations is more complex when spectra of different species overlap, but the problem can be solved by use of multiple analytical functions in combination with computational techniques that have been developed previously for analyses of this type. The method is applicable to the design and operation of a spectrometer in which spectrally dispersed light is measured by means of an active-pixel sensor (APS) array. The row or column dimension of such an array is generally chosen to be aligned along the spectral-dispersion dimension, so that each pixel intercepts light in a narrow spectral band centered on a wavelength that is a known function of the pixel position. The proposed method admits of two hardware implementations for computing cross-correlations in real time.

Beaman, Gregory↗

Design and implementation of scalable tape archiver

In order to reduce costs, computer manufacturers try to use commodity parts as much as possible. Mainframes using proprietary processors are being replaced by high performance RISC microprocessor-based workstations, which are further being replaced by the commodity microprocessor used in personal computers. Highly reliable disks for mainframes are also being replaced by disk arrays, which are complexes of disk drives. In this paper we try to clarify the feasibility of a large scale tertiary storage system composed of 8-mm tape archivers utilizing robotics. In the near future, the 8-mm tape archiver will be widely used and become a commodity part, since recent rapid growth of multimedia applications requires much larger storage than disk drives can provide. We designed a scalable tape archiver which connects as many 8-mm tape archivers (element archivers) as possible. In the scalable archiver, robotics can exchange a cassette tape between two adjacent element archivers mechanically. Thus, we can build a large scalable archiver inexpensively. In addition, a sophisticated migration mechanism distributes frequently accessed tapes (hot tapes) evenly among all of the element archivers, which improves the throughput considerably. Even with the failures of some tape drives, the system dynamically redistributes hot tapes to the other element archivers which have live tape drives. Several kinds of specially tailored huge archivers are on the market, however, the 8-mm tape scalable archiver could replace them. To maintain high performance in spite of high access locality when a large number of archivers are attached to the scalable archiver, it is necessary to scatter frequently accessed cassettes among the element archivers and to use the tape drives efficiently. For this purpose, we introduce two cassette migration algorithms, foreground migration and background migration. Background migration transfers cassettes between element archivers to redistribute frequently accessed cassettes, thus balancing the load of each archiver. Background migration occurs the robotics are idle. Both migration algorithms are based on access frequency and space utility of each element archiver. To normalize these parameters according to the number of drives in each element archiver, it is possible to maintain high performance even if some tape drives fail. We found that the foreground migration is efficient at reducing access response time. Beside the foreground migration, the background migration makes it possible to track the transition of spatial access locality quickly.

Nemoto, Toshihiro↗

NASA Small Spacecraft Technology (SST) Program - Recent and Upcoming Technology Demonstrations and Development Efforts

The Small Spacecraft Technology (SST) program within NASA’s Space Technology Mission Directorate, expands the ability to execute unique missions through rapid development and demonstration of capabilities for small spacecraft applicable to exploration, science and the commercial space sector. Through targeted development and frequent in space testing, the program: • Enables execution of missions at much lower cost than previously possible • Substantially reduces the time required for development of spacecraft • Enables new mission architectures through the use of small spacecraft • Expands the reach of small spacecraft to new destinations and challenging new environments • Enables the augmentation of existing assets and future missions with supporting small spacecraft. The program achieves its objectives through: • Identification and investment in the development of new subsystem technologies to enhance or expand the capabilities of small spacecraft • Sponsorship of flight demonstrations of new technologies, capabilities and applications for small spacecraft • Promotion of the use of small spacecraft as platforms for testing and demonstrating technologies and capabilities that might have more general applications in larger-scale spacecraft and systems Technologies funded by the program that are key to advancing the utility and capability of small spacecraft were demonstrated in 2022 and 2023. Notable on-orbit demonstrations include the following. • The Cislunar Autonomous Positioning System Technology Operations and Navigation Experiment’s (CAPSTONE) navigation technology that was demonstrated for the first time in 2023 could provide autonomous onboard navigation information for future lunar missions, minimizing or eliminating human-in-the-loop mission operations. • The optical communications technology also demonstrated in 2023 by the TeraByte InfraRed Delivery (TBIRD) payload that launched on Pathfinder Technology Demonstrator-3, achieved 200 gigabit per second (Gbps) throughput on a space-to-ground optical link between a satellite in orbit and Earth, the highest data rate ever achieved by optical communications technology. • The precision laser pointing performance of NASA’s CubeSat Infrared CrossLink A (CLICK) spacecraft’s fine steering mirror control system was successfully demonstrated. This element of the laser communications system will be used to demonstrate two-way crosslink communication in low-Earth orbit by CLICK B/C anticipated to launch in late 2024. Investments in subsystem technology development through funding to university, industry, and other government partners in a number of areas will be discussed. Among others, topic areas include propulsion, autonomous swarm technology, edge computing, and thermal control. Additionally, the status of the CubeSat-alternative platform, DiskSat, strategies for accelerating the demonstration of technology payloads via the Realizing Rapid, Reduced-cost high-Risk Research (R5) project, and the status of recently completed and upcoming on-orbit demonstrations will also be presented.

Roger C Hunter↗

On recursive least-squares filtering algorithms and implementations

In many real-time signal processing applications, fast and numerically stable algorithms for solving least-squares problems are necessary and important. In particular, under non-stationary conditions, these algorithms must be able to adapt themselves to reflect the changes in the system and take appropriate adjustments to achieve optimum performances. Among existing algorithms, the QR-decomposition (QRD)-based recursive least-squares (RLS) methods have been shown to be useful and effective for adaptive signal processing. In order to increase the speed of processing and achieve high throughput rate, many algorithms are being vectorized and/or pipelined to facilitate high degrees of parallelism. A time-recursive formulation of RLS filtering employing block QRD will be considered first. Several methods, including a new non-continuous windowing scheme based on selectively rejecting contaminated data, were investigated for adaptive processing. Based on systolic triarrays, many other forms of systolic arrays are shown to be capable of implementing different algorithms. Various updating and downdating systolic algorithms and architectures for RLS filtering are examined and compared in details, which include Householder reflector, Gram-Schmidt procedure, and Givens rotation. A unified approach encompassing existing square-root-free algorithms is also proposed. For the sinusoidal spectrum estimation problem, a judicious method of separating the noise from the signal is of great interest. Various truncated QR methods are proposed for this purpose and compared to the truncated SVD method. Computer simulations provided for detailed comparisons show the effectiveness of these methods. This thesis deals with fundamental issues of numerical stability, computational efficiency, adaptivity, and VLSI implementation for the RLS filtering problems. In all, various new and modified algorithms and architectures are proposed and analyzed; the significance of any of the new method depends crucially on specific application.

Hsieh, Shih-Fu↗

HTMT-class Latency Tolerant Parallel Architecture for Petaflops Scale Computation

Computational Aero Sciences and other numeric intensive computation disciplines demand computing throughputs substantially greater than the Teraflops scale systems only now becoming available. The related fields of fluids, structures, thermal, combustion, and dynamic controls are among the interdisciplinary areas that in combination with sufficient resolution and advanced adaptive techniques may force performance requirements towards Petaflops. This will be especially true for compute intensive models such as Navier-Stokes are or when such system models are only part of a larger design optimization computation involving many design points. Yet recent experience with conventional MPP configurations comprising commodity processing and memory components has shown that larger scale frequently results in higher programming difficulty and lower system efficiency. While important advances in system software and algorithms techniques have had some impact on efficiency and programmability for certain classes of problems, in general it is unlikely that software alone will resolve the challenges to higher scalability. As in the past, future generations of high-end computers may require a combination of hardware architecture and system software advances to enable efficient operation at a Petaflops level. The NASA led HTMT project has engaged the talents of a broad interdisciplinary team to develop a new strategy in high-end system architecture to deliver petaflops scale computing in the 2004/5 timeframe. The Hybrid-Technology, MultiThreaded parallel computer architecture incorporates several advanced technologies in combination with an innovative dynamic adaptive scheduling mechanism to provide unprecedented performance and efficiency within practical constraints of cost, complexity, and power consumption. The emerging superconductor Rapid Single Flux Quantum electronics can operate at 100 GHz (the record is 770 GHz) and one percent of the power required by convention semiconductor logic. Wave Division Multiplexing optical communications can approach a peak per fiber bandwidth of 1 Tbps and the new Data Vortex network topology employing this technology can connect tens of thousands of ports providing a bi-section bandwidth on the order of a Petabyte per second with latencies well below 100 nanoseconds, even under heavy loads. Processor-in-Memory (PIM) technology combines logic and memory on the same chip exposing the internal bandwidth of the memory row buffers at low latency. And holographic storage photorefractive storage technologies provide high-density memory with access a thousand times faster than conventional disk technologies. Together these technologies enable a new class of shared memory system architecture with a peak performance in the range of a Petaflops but size and power requirements comparable to today's largest Teraflops scale systems. To achieve high-sustained performance, HTMT combines an advanced multithreading processor architecture with a memory-driven coarse-grained latency management strategy called "percolation", yielding high efficiency while reducing the much of the parallel programming burden. This paper will present the basic system architecture characteristics made possible through this series of advanced technologies and then give a detailed description of the new percolation approach to runtime latency management.

Sterling, Thomas↗

Space Biotech: Hindsight, Insight, Foresight

Over the past forty years, microgravity has inspired and enabled applications in a wide range of sectors including medicine, materials, computers, communications, and national defense. Trends show that demand for high-tech solutions is increasing in these sectors, solutions that require higher resolution, greater precision, novel materials, innovative processes, and more sophisticated tools. These are areas where microgravity can offer unique capabilities for innovation. The Emerging Space Office (ESO) has engaged in multiple studies over the past year that have found that microgravity RD is one of the most promising technology areas for contributing to economic growth and to NASAs mission. The focus of these studies was on terrestrial markets rather than NASA applications, applied research rather than basic research, and commercial rather than academic investigators. There have been more success stories than are generally appreciated and there are significant areas of promising future potential. Many of the problems that have limited commercial microgravity development in the past are being solved. Microgravity research and development (RD) requires iteration and learning, as rapidly as possible. New technologies enable high throughput and rapid data collection in increasingly small payloads. The International Space Station is in orbit and provides a laboratory that is available 247 at least until 2024. Frequent flights by commercial space providers to and from the ISS now enable the fast learning cycles needed by high-tech industries. Launch costs are decreasing and the ability to return payloads to Earth is increasing. New commercial space laboratories, such as those being developed by SpaceX and Bigelow Aerospace, are in the final stages of development and testing. This ecosystem for microgravity RD has never been available before. These are game-changer conditions for attracting high-tech industries to space for terrestrial, as well as NASA, applications. However, few know that these capabilities are available or how to use them. In aggregate, the potential value for new applications from microgravity RD over the next ten years could add billions of dollars per year in terrestrial applications to the future economy, create new jobs, and generate a wide range of public benefits in medical advances, while broadening the customer base for the emerging space industry.

biotech↗

Data storage and retrieval system abstract

The STX mass storage system design is intended for environments requiring high speed access to large volumes of data (terabyte and greater). Prior to commitment to a product design plan, STX conducted an exhaustive study of the commercially available off-the-shelf hardware and software. STX also conducted research into the area of emerging technologies in networks and storage media so that the design could easily accommodate new interfaces and peripherals as they came on the market. All the selected system elements were brought together in a demo suite sponsored jointly by STX and ALLIANT where the system elements were evaluated based on actual operation using a client-server mirror image configuration. Testing was conducted to assess the various component overheads and results were compared against vendor data claims. The resultant system, while adequate to meet our capacity requirements, fell short of transfer speed expectations. A product team lead by STX was assembled and chartered with solving the bottleneck issues. Optimization efforts yielded a 60 percent improvement in throughput performance. The ALLIANT computer platform provided the I/O flexibility needed to accommodate a multitude of peripheral interfaces including the following: up to twelve 25MB/s VME I/O channels; up to five HiPPI I/O full duplex channels; IPI-s, SCSI, SMD, and RAID disk array support; standard networking software support for TCP/IP, NFS, and FTP; open architecture based on standard RISC processors; and V.4/POSIX-based operating system (Concentrix). All components including the software are modular in design and can be reconfigured as needs and system uses change. Users can begin with a small system and add modules as needed in the field. Most add-ons can be accomplished seamlessly without revision, recompilation or re-linking of software.

Matheson, Barbara↗

Performance Optimization Methods for a Memory-Bound, Unstructured-Grid CFD Application on Massively Parallel GPU Platforms

Computational performance of the FUN3D unstructured-grid computational fluid dynamics (CFD) application on massively parallel GPU environments is memory-bound and highly dependent upon efficient reads from and atomic updates to the irregular cell-, edge-, and node-based data structures. In this talk, we present recent efforts into optimizing select performance-critical kernels on NVIDIA Tesla V100 and A100 GPUs and AMD CDNA MI100 GPUs. A novel use of L2 cache residency controls and asynchronous loads into on-chip shared memory are explored on the A100 GPU for the sparse iterative solver, which is dominated by mixed-precision, sparse matrix vector multiplication. Demonstrations show that these methods improve global memory bandwidth utilization by 13.5% on the A100 GPU. Several techniques are also presented that use registers and/or shared memory to facilitate array transposition and aggregation which combine to reduce the frequency and increase the cache efficiency of floating-point atomic updates to the irregular data structures. These methods are demonstrated to improve the kernel throughput by nearly 500% on select kernels on the AMD MI100 over atomic updates directly to global memory. Overall, both V100 and A100 GPUs outperformed the MI100 GPU on kernels dominated by double-precision atomic updates; however, the techniques demonstrated here reduced the performance gap and improved the MI100 performance.

GPU CPU unstructured CFD memory↗

Implementation of Pin Point Landing Vision Components in an FPGA System

Pin-point landing is required to enable missions to land close, typically within 10 meters, to scientifically important targets in generally hazardous terrain. In Pin Point Landing both high accuracy and high speed estimation of position and orientation is needed to provide input to the control system to safely choose and navigate to a safe landing site. A proposed algorithm called VISion aided Inertial NAVigation (VISINAV) has shown that the accuracy requirements can be met. [2][3] VISINAV was shown in software only, and was expected to use FPGA enhancements in the future to improve the computational speed needed for pin point landing during Entry Descent and Landing (EDL). Homography, feature detection and spatial correlation are computationally intensive parts of VISINAV. Homography aligns the map image with the descent image so that small correlation windows can be used, and feature detection provides regions that spatial correlation can track from frame to frame in order to estimate vehicle motion. On MER the image Homography, Feature Detection and Correlation would take approximately 650ms tracking 75 features between frames. We implemented Homography, Feature detection and Correlation on a Virtex 4 LX160 FPGA to run in under 25ms while tracking 500 features to improve algorithm reliability and throughput.

aircraft landing guidance↗

Design of a real-time wind turbine simulator using a custom parallel architecture

The design of a new parallel-processing digital simulator is described. The new simulator has been developed specifically for analysis of wind energy systems in real time. The new processor has been named: the Wind Energy System Time-domain simulator, version 3 (WEST-3). Like previous WEST versions, WEST-3 performs many computations in parallel. The modules in WEST-3 are pure digital processors, however. These digital processors can be programmed individually and operated in concert to achieve real-time simulation of wind turbine systems. Because of this programmability, WEST-3 is very much more flexible and general than its two predecessors. The design features of WEST-3 are described to show how the system produces high-speed solutions of nonlinear time-domain equations. WEST-3 has two very fast Computational Units (CU's) that use minicomputer technology plus special architectural features that make them many times faster than a microcomputer. These CU's are needed to perform the complex computations associated with the wind turbine rotor system in real time. The parallel architecture of the CU causes several tasks to be done in each cycle, including an IO operation and the combination of a multiply, add, and store. The WEST-3 simulator can be expanded at any time for additional computational power. This is possible because the CU's interfaced to each other and to other portions of the simulation using special serial buses. These buses can be 'patched' together in essentially any configuration (in a manner very similar to the programming methods used in analog computation) to balance the input/ output requirements. CU's can be added in any number to share a given computational load. This flexible bus feature is very different from many other parallel processors which usually have a throughput limit because of rigid bus architecture.

Hoffman, John A.↗

Overview of Variable-Speed Power-Turbine Research

The vertical take-off and landing (VTOL) and high-speed cruise capability of the NASA Large Civil Tilt-Rotor (LCTR) notional vehicle is envisaged to enable increased throughput in the national airspace. A key challenge of the LCTR is the requirement to vary the main rotor speeds from 100% at take-off to near 50% at cruise as required to minimize mission fuel burn. The variable-speed power-turbine (VSPT), driving a fixed gear-ratio transmission, provides one approach for effecting this wide speed variation. The key aerodynamic and rotordynamic challenges of the VSPT were described in the FAP Conference presentation. The challenges include maintaining high turbine efficiency at high work factor, wide (60 deg.) of incidence variation in all blade rows due to the speed variation, and operation at low Reynolds numbers (with transitional flow). The PT -shaft of the VSPT must be designed for safe operation in the wide speed range required, and therefore poses challenges associated with rotordynamics. The technical challenges drive research activities underway at NASA. An overview of the NASA SRW VSPT research activities was provided. These activities included conceptual and preliminary aero and mechanical (rotordynamics) design of the VSPT for the LCTR application, experimental and computational research supporting the development of incidence tolerant blading, and steps toward component-level testing of a variable-speed power-turbine of relevance to the LCTR application.

Welch, Gerard E.↗

The Goddard High Resolution Spectrograph Scientific Support Contract

In 1988, Computer Sciences Corporation (CSC) was selected as the Goddard High Resolution Spectrograph (GHRS) Scientific Support Contractor (SSC). This was to have been a few months before the launch of NASA's first Great Observatory, the Hubble Space Telescope (HST). As one of five scientific instruments on HST, the GHRS was designed to obtain spectra in the 1050-3300 A ultraviolet wavelength region with a resolving power, lambda/Delta(lambda) , of up to 100,000 and relative photometric accuracy to 1%. It was built by Ball AeroSpace Systems Group under the guidance of the GHRS Investigation Definition Team (IDT), comprised of 16 scientists from the US and Canada. After launch, the IDT was to perform the initial instrument calibration and execute a broad scientific program during a five-year Guaranteed Time Observation (GTO) period. After a year's delay, the launch of HST occurred in April 1990, and CSC participated in the in-orbit calibration and first four years of GTO observations with the IDT. The HST primary mirror suffered from spherical aberration, which reduced the spatial and spectral resolution of Large Science Aperture (LSA) observations and decreased the throughput of the Small Science Aperture (SSA) by a factor of two. Periodic problems with the Side 1 carrousel electronics and anomalies with the low-voltage power supply finally resulted in a suspension of the use of Side 1 less than two years after launch. At the outset, the GHRS SSC task involved work in four areas: 1) to manage and operate the GHRS Data Analysis Facility (DAF); 2) to support the second Servicing Mission Observatory Verification (SMOV) program, as well as perform system engineering analysis of the GHRS as nesessary; 3) to assist the GHRS IDT with their scientific research programs, particularly the GSFC members of the team, and 4) to provide administrative and logistic support for GHRS public information and educational activities.

Source record↗

An Integrated Architecture for Onboard Spacecraft

As increasingly complex scientific and environmental observation spacecraft are deployed, the burden on the downlink assets, and ground-based systems complexity and cost is becoming a major problem. Already, the limitations of communications bandwidth and processing throughput limit the science data gathering, both in volume and in rate. This poses a dilemma to the scientist experimenter forcing choices between data collection and bandwidth/processing/archiving. Advances in ground based processing and space-to-Earth links have fallen behind the requirements for observation data, at increasing rates, over the last few decades. As NASA achieves its 40th anniversary, the ability to observe and capture phenomena of theoretical and practical interest to life on Earth far outstrips the ability to transfer, process, or store these data. NASA recognizes the need to invest on technological advancements that will enable both the space and ground systems to address the limitations. Spacecraft onboard computing power is a clear one. The capability of creating data products onboard the spacecraft adds a new level of flexibility to address the more demanding observation needs. Current spacecraft computing power is limited and incapable of addressing the needs of the new generation of observation satellites because extensive onboard data processing is required. Traditional spacecraft architectures only collect, package, and transmit to Earth the data acquired by multiple instruments. Conversely, the experience on developing ground data systems shows the need for high performance computing systems to process and create information from the instrumentation data. The expectation is that supercomputing technology is required to enable spacecraft to create information onboard. Moving supercomputing capability onboard spacecraft requires an approach that considers an integrated data architecture. Otherwise, it may simply convert a compute-bound problem into a communications bound problem, as has been shown numerous times in the context of massively parallel architectures. What is left to determine are the technologies that will enable spacecraft high performance computing.

Figueiredo, Marco A.↗

Materials Informatics at NASA GRC: Machine Learning Surrogate Modeling, Data Management, and Integrated Toolsets for Establishing/Maintaining the Digital Thread

Integrated Computational Materials Engineering (ICME) has recently received widespread attention due to its promises in reducing dependence on physical testing for engineering design by relying on simulation, reducing both time and cost to market for various applications. ICME however requires validated multiscale material models, which heavily depend on available test data with full material and test pedigree, including material processing, test and measurement equipment, raw data collection, and analysis methodology and results that is findable and usable, along with integrated, efficient toolsets for effectively passing information across various length and time scales across such models. At the NASA Glenn Research Center under the Transformational Tools and Technologies Project, significant recent efforts have been directed towards establishing the required cyberinfrastructure to enable optimized ICME processes and the design of “fit-for-purpose” materials to achieve the goals outlined in the NASA Vision 2040 report. Such efforts include development of multiscale physics-based material models, which can be used to train highly efficient surrogate machine learning models, development of best practices and infrastructure for effective, traceable materials information management, and development of toolsets that integrate with physics-based codes, machine learning models, and an information management system to enable high throughput of materials data collection and analysis, establishment of digital twins and the digital thread, and automation of the ICME design process for material optimization.

Machine Learning↗