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At least 127 records · Page 7

Selective consolidation of learning and memory via recall-gated plasticity

In a variety of species and behavioral contexts, learning and memory formation recruits two neural systems, with initial plasticity in one system being consolidated into the other over time. Moreover, consolidation is known to be selective; that is, some experiences are more likely to be consolidated into long-term memory than others. Here, we propose and analyze a model that captures common computational principles underlying such phenomena. The key component of this model is a mechanism by which a long-term learning and memory system prioritizes the storage of synaptic changes that are consistent with prior updates to the short-term system. This mechanism, which we refer to as recall-gated consolidation, has the effect of shielding long-term memory from spurious synaptic changes, enabling it to focus on reliable signals in the environment. We describe neural circuit implementations of this model for different types of learning problems, including supervised learning, reinforcement learning, and autoassociative memory storage. These implementations involve synaptic plasticity rules modulated by factors such as prediction accuracy, decision confidence, or familiarity. We then develop an analytical theory of the learning and memory performance of the model, in comparison to alternatives relying only on synapse-local consolidation mechanisms. We find that recall-gated consolidation provides significant advantages, substantially amplifying the signal-to-noise ratio with which memories can be stored in noisy environments. We show that recall-gated consolidation gives rise to a number of phenomena that are present in behavioral learning paradigms, including spaced learning effects, task-dependent rates of consolidation, and differing neural representations in short- and long-term pathways.

Lindsey, Jack W. (ORCID:0000000309307327)↗

P-channel silicone gate FET

Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.

Ostis, S.↗

Process development of beam-lead silicon-gate COS/MOS integrated circuits

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Baptiste, B.↗

Testing the linearity of response of gated photomultipliers in wide dynamic range laser radar systems

Laser radar data acquisition systems have been utilized in conjunction with a light emitting diode to evaluate photomultipliers for laser radar use. Light pulses with an exponential decay rate of approximately one decade per sixty microseconds, as well as other pulse shapes, were used to drive the tubes. Properties studied in the analog mode include nonlinearity at high output currents, transient behavior upon gating, gate holdoff, dynamic range limitations because of light-induced noise, and the effect of dynode gating on tubes without a focus grid. Some of these properties were also studied in the photon counting mode, along with single photoelectron pulse shape and afterpulsing. A brief description of the laser radar technique of atmospheric measurements is included.

Hunt, W. H.↗

Gate-assisted turnoff thyristors

A study of the turnoff physics in gate-assisted turnoff thyristors (GATT's) leads to a proposed mechanism involving the gate bias acting to prevent a forward voltage from appearing on the cathode rather than, as was previously thought, to sweep out excess carriers. It is shown that cathode shunting can be used in GATT's to virtually eliminate an important failure mode and to decrease the gate voltage needed to produce the desired improvement in turnoff time. Implications for designing GATT's are given, one being that a change in the lateral resistance of the p-base will have opposite effects depending on whether the cathode is shunted or not.

Schlegel, E. S.↗

Gate-assisted turn-off thyristor

1,000-volt, 200-ampere gate-assisted turn-off thyristor has been developed for power circuits requiring high efficiency, small size, and low weight. Design features include shunted cathode for high dV/dt capability. Cathode in interdigitated with dynamic gate for fast, low-loss switching. Operating frequency exceeds 20 kHz with overall energy dissipation of less that 12 mJ per pulse for typical 20-microsecond half-sine waveform. Device has turn-on time of 2 microseconds and turn-off time as short as 3 microseconds with only 2 amperes of gate drive.

Lowry, L. R.↗

Velocity overshoot effect on a short-gate microwave MESFET

The device parameters of short-gate GaAs and InP FETs have been found to be dependent on the nonequilibrium velocity overshoot phenomenon. Both saturation velocity and critical field are found to be larger for shorter gates. The v-E characteristics of Pucel et al. (1975) are modified. The cutoff frequency and other parameters for GaAs, InP, and Si are given as a function of gate length and bias. The cutoff frequency of InP MESFETs with a doping density of 10 to the 17th per cu cm is only 20% higher than those of equivalent GaAs MESFETs at 300 K. Comparison with other work is also presented.

Wang, Y.-C.↗

Ultrasonic spectrum analysis using frequency-tracked gated RF pulses

A new method of ultrasonic frequency analysis is introduced which employs frequency-tracked gated RF drive pulses rather than shock-excited broadband spikes to generate the ultrasonic waveform. The new technique, a variation of the sampled-continuous wave technique, eliminates problems associated with finite pulse widths of conventional methods. It is shown to yield correct ultrasonic wave velocity measurements of the sample irrespective of receiver gate width or position provided any portions of two successive echoes are gated simultaneously into the spectrum analyzer. The experimental observations are substantiated by a theoretical model based on the time-frequency domain formulation of ultrasonic frequency analysis.

Cantrell, J. H., Jr.↗

A new planar injection-gated bulk switching device based upon deep impurity trapping

Under the proper conditions, double-injection (DI) diodes with partially compensated deep impurities will exhibit 'S'-type switching characteristics similar to conventional silicon-controlled rectifiers (SCR's). A practical injection-gating scheme has been achieved for the first time in a planar configuration to control the switching behavior of these devices, marked by extreme sensitivity of the gate over a range of switching voltages. An experiment to demonstrate the feasibility of these devices for practical application is described. Finally, a phenomenological explanation is presented for the gate-controlled switching of these devices.

Kapoor, A. K.↗

Equivalent-circuit consideration of dual-gate MESFETs at high frequency

The simplified high-frequency equivalent circuit of a dual-gate FET is described. It is shown that the input impedance is similar to that of a single-gate FET but the output resistance and capacitance (parallel equivalent circuit) are higher. The output resistance and the transconductance decrease as frequency increases. The unilateral gain of a dual-gate FET rolls off 12 dB/octave.

Kim, B.↗

Optical Logic Gates

Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.

Du Fresne, E. R.↗

System Measures Logic-Gate Delays

Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.

Blaes, Brent R.↗

Remote gate capacitance-voltage studies for noninvasive surface characterization

A measurement technique has been developed which allows noncontact capacitance-voltage measurements to be made using a gate electrode located remote from the semiconductor surface under study. With gate electrodes about 0.5 mm in diameter and gate to semiconductor separations of about 1500 A, it was possible to generate data entirely comparable to that obtained with integrated MIS structures but with the advantage that there was access directly to the free-semiconductor surface. This technique was applied to bulk single-crystal Si and InP samples.

Chang, R. R.↗

GetAway Tether Experiment (GATE) for the Tether Dynamics Explorer (TDE) series

Designs for the GetAway Tether Experiment (GATE) can easily be adapted and applied to the Tether Dynamics Explorer (TDE) series. The GATE development schedule coincides with the planned first flight of the TDE. GATE technology has centered on the development of miniature deployers/actuators, sensors, control laws and simulation capability. The sensors currently under development are a tension sensor and a video based tether tracker. Both sensors are currently undergoing laboratory testing and development. The actuators currently being investigated are a small reel/deployed for active control of the tether and a small tether crawler to damp vibrations of the tether. Laboratory results are presented and the designs reviewed and discussed.

Greene, Michael↗

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

Kapoor, V. J.↗

Radiation Issues and Applications of Floating Gate Memories

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

Scheick, L. Z.↗

Energetic and spatial parameters for gating of the bacterial large conductance mechanosensitive channel, MscL

MscL is multimeric protein that forms a large conductance mechanosensitive channel in the inner membrane of Escherichia coli. Since MscL is gated by tension transmitted through the lipid bilayer, we have been able to measure its gating parameters as a function of absolute tension. Using purified MscL reconstituted in liposomes, we recorded single channel currents and varied the pressure gradient (P) to vary the tension (T). The tension was calculated from P and the radius of curvature was obtained using video microscopy of the patch. The probability of being open (Po) has a steep sigmoidal dependence on T, with a midpoint (T1/2) of 11.8 dyn/cm. The maximal slope sensitivity of Po/Pc was 0.63 dyn/cm per e-fold. Assuming a Boltzmann distribution, the energy difference between the closed and fully open states in the unstressed membrane was DeltaE = 18.6 kBT. If the mechanosensitivity arises from tension acting on a change of in-plane area (DeltaA), the free energy, TDeltaA, would correspond to DeltaA = 6.5 nm2. MscL is not a binary channel, but has four conducting states and a closed state. Most transition rates are independent of tension, but the rate-limiting step to opening is the transition between the closed state and the lowest conductance substate. This transition thus involves the greatest DeltaA. When summed over all transitions, the in-plane area change from closed to fully open was 6 nm2, agreeing with the value obtained in the two-state analysis. Assuming a cylindrical channel, the dimensions of the (fully open) pore were comparable to DeltaA. Thus, the tension dependence of channel gating is primarily one of increasing the external channel area to accommodate the pore of the smallest conducting state. The higher conducting states appear to involve conformational changes internal to the channel that don't involve changes in area.

Non-NASA Center↗