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Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.
The present study, based on a NASA technology assessment, examines the effect of new technologies on trends in crew-systems design and their implications from the vantage point of man-vehicle systems research. Those technologies that are most relevant to future trends in crew-systems design are considered along with problems associated with the introduction of rapidly changing technologies and systems concepts from a human-factors point of view. The technologies discussed include information processing, displays and controls, flight and propulsion control, flight and systems management, air traffic control, training and simulation, and flight and resource management. The historical evolution of cockpit systems design is used to illustrate past and possible future trends in man-vehicle systems research.
Techniques developed for producing fault-tolerant software are described. Tolerance is required because of the impossibility of defining fault-free software. Faults are caused by humans and can appear anywhere in the software life cycle. Tolerance is effected through error detection, damage assessment, recovery, and fault treatment, followed by return of the system to service. Multiversion software comprises two or more versions of the software yielding solutions which are examined by a decision algorithm. Errors can also be detected by extrapolation from previous results or by the acceptability of results. Violations of timing specifications can reveal errors, or the system can roll back to an error-free state when a defect is detected. The software, when used in flight control systems, must not impinge on time-critical responses. Efforts are still needed to reduce the costs of developing the fault-tolerant systems.
The concept of Boolean integration is introduced and developed. When the changes in a desired function are specified in terms of changes in its arguments, then ways of 'integrating' (i.e., realizing) the function, if it exists, are presented. Boolean integral calculus has applications in design of logic circuits.
This paper outlines a candidate design and assessment methodology that is targeted for the early to mid-level phases of the design cycle. This method allows alternate architectural configurations to be effectively assessed to evaluate the effects of design changes and to reduce the number of inherent design errors.
Three theorems which show that the reliability of a popular class of systems can be computed using small and simple models are presented. This class consists of systems that are assemblages of subsystems where each subsystem is a majority-voting threeplex plus spares or majority-voting fourplex plus spares. The theorems are error bounds for model reduction and simplification. The error bounds are given in terms of readily available system parameters. The three theorems have been applied to a system that has been used as an example that generates extremely large reliability models; the system considered is one version of AIPS (Advanced Information Processing System) for IAPSA (Integrated Airframe Propulsion System Architecture).
Alternatives for realizing a packet-based network switch for use on a frequency division multiple access/time division multiplexed (FDMA/TDM) geostationary communication satellite were investigated. Each of the eight downlink beams supports eight directed dwells. The design needed to accommodate multicast packets with very low probability of loss due to contention. Three switch architectures were designed and analyzed. An output-queued, shared bus system yielded a functionally simple system, utilizing a first-in, first-out (FIFO) memory per downlink dwell, but at the expense of a large total memory requirement. A shared memory architecture offered the most efficiency in memory requirements, requiring about half the memory of the shared bus design. The processing requirement for the shared-memory system adds system complexity that may offset the benefits of the smaller memory. An alternative design using a shared memory buffer per downlink beam decreases circuit complexity through a distributed design, and requires at most 1000 packets of memory more than the completely shared memory design. Modifications to the basic packet switch designs were proposed to accommodate circuit-switched traffic, which must be served on a periodic basis with minimal delay. Methods for dynamically controlling the downlink dwell lengths were developed and analyzed. These methods adapt quickly to changing traffic demands, and do not add significant complexity or cost to the satellite and ground station designs. Methods for reducing the memory requirement by not requiring the satellite to store full packets were also proposed and analyzed. In addition, optimal packet and dwell lengths were computed as functions of memory size for the three switch architectures.
A timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems was developed in this work. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modify the circuit clock period.
The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.
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