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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Site 2 of the Yersinia pestis substrate-binding protein YfeA is a dynamic surface metal-binding site

The substrate-binding protein YfeA (also known as YPO2439 or y1897) is a polyspecific metal-binding protein that is crucial for nutrient acquisition and virulence in Yersinia pestis, the causative microbe of plague. YfeA folds into a monomeric c-clamp like other substrate-binding proteins and has two metal-binding sites (sites 1 and 2). Site 2 is a bidentate surface site capable of binding Zn and Mn atoms and is a unique feature of YfeA. Occasionally, the site 2 residues of two YfeA molecules will cooperate with the histidine tag of a third YfeA molecule in coordinating the same metal and lead to metal-dependent crystallographic packing. Here, three crystal structures of YfeA are presented at 1.85, 2.05 and 2.25 Å resolution. A comparison of the structures reveals that the metal can be displaced at five different locations ranging from ~4 to ~16 Å away from the canonical site 2. These observations reveal different configurations of site 2 that enable cooperative metal binding and demonstrate how site 2 is dynamic and freely available for inter-protein metal coordination.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Interpolation Methods to Enable Fast and Accurate EMT Simulation of PV Inverters

In this paper, interpolation methods to enable fast simulation of photovoltaic (PV) inverters are proposed. The interpolation methods are based on the event-driven interpolating method that can be introduced in the simulation model to run the model at a higher timestep while maintaining accuracy. The proposed methods are tested on a neutral point clamp (NPC) converter and a two-level converter (2LC) that are typically used in large-scale PV plants. The interpolation methods are integrated into the NPC and 2LC simulation models in PSCAD/Fortran and RSCAD C platforms. These models are tested at different simulation timesteps in off-line and real-time simulation platforms PSCAD and RSCAD respectively.

Marthi, Phani Ratna Vanamali↗
DOE OSTI2022

Digital Twin of an ANPC inverter with integrated Design-For-Trust

Reducing costs and increasing manufacturing output while creating reliable products are three essential components needed to keep a business competitive. In the past, having an asset that could address these three challenges at the same time would be challenging. However, recent advances in computer processing capabilities coupled with increases to network speeds allowed such a system to become possible; and this is known as a Digital Twin (DT), which represents a virtual copy of a production system or a product. Here, this work exhibits a DT application of an Active Neutral Point Clamped (ANPC) inverter using a controller. The controller emulates the ANPC responses of a new Digital Signal Processing (DSP) firmware and validates this new firmware by using Design-For-Trust (DFTr) characteristics. If the new firmware is malicious, then it should be rejected, thus adding preemptive protection measures for inverter based distributed energy resources.

cybersecurity↗
DOE OSTI2020

A Simplified Model Predictive Control Strategy for a Nine-Level Hybrid Multilevel Converter

This paper proposes a simplified model predictive control (SMPC) for a 9-level hybrid multilevel converter based on the active-neutral-point-clamped (ANPC) topology. The proposed SMPC firstly identifies the voltage vector that has optimal current tracking performance by a novel geometrical positioning approach in the complex plane, which can dramatically reduce the computational burden. Then it evaluates the switching states that are subject to the same voltage vector and selects the optimal switching state to balance the dc capacitor voltages. Both simulation and experimental results are carried out to validate the feasibility and effectiveness of the proposed control strategy.

14 SOLAR ENERGY↗
DOE OSTI2020

Comparison of Dead-Time Effects in a WPT System Inverter for Different Fixed-Frequency Modulation Techniques

In this paper, a comparative study of the dead-time effects in a wireless power transfer (WPT) system inverter is performed for different fixed-frequency control techniques. The dead-time is provided between the complementary switching instances of the inverter phase-legs to ensure safe operation of the input power source. Under certain operating conditions, the dead-time results in waveform distortions or voltage-polarity reversal (VPR) at the inverter output. The VPR affects the switching characteristics, harmonic spectrum, switching losses, and output voltage/power of the system. A detailed analysis of the dead-time effect on the WPT system parameters such as output voltage and output power is conducted for the different fixed-frequency control strategies (i.e., traditional phase-shift control, asymmetrical clamped-mode, and asymmetrical duty-cycle control). Furthermore, the impact of dead-time on the inverter switching losses is compared for the different control strategies.

Kavimandan, Utkarsh↗
DOE OSTI2025

Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation

This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.

Lee, Sangwhee [ORNL] (ORCID:0000000335490057)↗
DOE OSTI2023

A Voltage Injection-Based Current Harmonics Suppression Strategy for Six-Phase PMSM With Nonsinusoidal Back EMF

This article presents a voltage injection-based current harmonic minimization method for wide bandgap device-based six-phase permanent magnet synchronous machine (PMSM) drives. The presence of low-order harmonics is common in the back EMF of PMSMs with low slot and high pole numbers. The back EMF harmonics generate low-order harmonic currents that increase torque ripples. Furthermore, zero-sequence current (ZSC) is also observed if all six phases are connected to a common neutral point. ZSC does not affect the torque ripple but reduces the system efficiency. A special technique is required to reduce ZSC for variable speed drives as direct ac component to synchronous reference frame (SRF) dc transformation is not possible for ZSC. In this article, a voltage injection-based current harmonics reduction method is proposed. The injected harmonic voltage coefficients are calculated from the harmonic estimations of back EMF and updated using closed-loop harmonic compensators to improve steady-state performance. For ZSC reduction, third harmonics power controller, and for 6n ± 1 (n = 1, 2,...) order harmonic current reduction, SRF current controllers are presented in this article. Furthermore, the current harmonics minimization method is experimentally verified using a GaN-based three-level active neutral point clamped inverter-driven six-phase PMSM.

42 ENGINEERING↗
DOE OSTI2020

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗
DOE OSTI2024

Experiences and Lessons from Field Demonstration of Grid-forming Inverter in An AC Microgrid

The validation of GFM control strategies through simulation and hardware demonstration is important before their large-scale deployments in the real grid. Considering the importance of testing and validation, several works have explored the GFM inverter’s capability to blackstart a microgrid, synchronize and share loads, and interact with various types of generation sources and loads present in the grid. Herein, this paper complements the existing works by presenting the results and analysis of a field demonstration in an actual AC microgrid. The capability of a three-level neutral point clamped (NPC) GFM inverter equipped with a recursive feedback type of non-linear device level control to operate with PV source on its DC input and off-the-shelf PVGFL inverters and EV chargers of different kinds on the AC side is explored. The analysis and conclusions drawn would inform the readers to make better decisions during the field demonstration process.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Implementing a Hardware Testbed Using 3-Level ANPC Software Defined Inverters for Fault Analysis of a Transmission Network

In this paper, we propose the implementation of a hardware testbed using 3-level active neutral point clamped (ANPC) software-defined inverters for fault analysis. A test case transmission network equipped with two grid forming (GFM) inverters and four resistive loads is considered in this research. Firstly, grid forming control laws including PI feedback control and droop control are implemented to operate the inverters in parallel. Then, we implement a fault ride-through (FRT) logic and perform a simulation of the test system by applying a three-phase fault. Simulation results show the effectiveness of the fault recovery algorithm upon clearance of the fault. Finally, a 3-level ANPC software-defined inverter is programmed with required control laws and characterized through various lab experiments.

3-level ANPC inverter↗
DOE OSTI2020

Development and First Test of the 15 T Nb$_3$Sn Dipole Demonstrator MDPCT1

Fermilab in the framework of the U.S. Magnet Devel-opment Program (MDP) has developed a Nb$_3$Sn dipole demonstrator for a post-LHC hadron collider. The magnet uses 60-mm aperture 4-layer shell-type graded coils. The cable in the two inner-most layers has 28 strands 1.0 mm in diameter and the cable in the two outermost layers has 40 strands 0.7 mm in diameter. An inno-vative mechanical structure based on aluminum I-clamps and a thick stainless steel skin is used to preload Nb$_3$Sn coils and support large Lorentz forces. The maximum field for this magnet is limited by 15 T due to mechanical considerations. The first magnet assembly was done with lower coil pre-load to achieve 14 T and minimize the risk of coil damage during assembly. This paper describes the magnet design and the details of its assembly procedure, and re-ports the results of its cold tests.

43 PARTICLE ACCELERATORS↗
DOE OSTI2020

First Field Measurements of the 15 T Nb 3 Sn Dipole Demonstrator MDPCT1

Within the US Magnet Development Program (MDP) a 15 T Nb 3 Sn dipole was developed, to demonstrate a magnet design for a post-LHC pp Collider. Specifically, the magnet design is based on 60 mm aperture 4-layer shell-type coils, graded between the inner and outer layers to maximize the magnet performance. The cable in the two innermost layers has 28 strands 1.0 mm in diameter and the cable in the two outermost layers has 40 strands 0.7 mm in diameter. Both cables use RRP Nb3Sn wires produced by Bruker-OST. Magnet coils are surrounded by vertically-split thick iron laminations, con-nected by aluminum I-clamps, and a thick stainless-steel skin. The magnet was tested at the Vertical Magnet Test Facility (VMTF) at Fermilab. This paper reports the first results of magnetic measure-ments of the 15 T Nb 3 Sn dipole demonstrator including geometrical harmonics, coil magnetization and iron saturation effects. The ex-perimental data are compared with the magnetic calculations.

43 PARTICLE ACCELERATORS↗
DOE OSTI2022

Novel Quadratic High Gain Boost Converter With Adaptive Soft-Switching Scheme and Reduced Conduction Loss

In this article, an improved soft-switching quadratic boost converter is proposed. Instead of inserting an additional active clamp or auxiliary zero-voltage transition circuit at the switching node, the proposed topology connects the high-voltage switching node to the input diode node by replacing one of the input diodes with a low-rated switch. The proposed topology can attain soft-switching condition for all the switches and input diode turns- off under zero-current switching (ZCS). The operation of input-side switch not only aids zero-voltage switching (ZVS) turn- on for the main switch but also helps in reducing the conduction loss. Also, the input-side switch operates under ZCS turn- on and ZVS turn- off , making it a loss economical solution. An adaptive timing scheme for driving the input switch is proposed, which can ensure soft-switching condition under varying gain and load range. The detailed operational modes, analysis, and design considerations of the proposed topology are presented. A 250 W hardware prototype is built to validate the performance of the proposed converter operating at 100 kHz switching frequency. Results with adaptive soft-switching scheme shows that the converter is modulated to achieve its best efficiency condition under various system conditions. Furthermore, a peak efficiency of 96.1% at 155 W and efficiencies above 95.75% over a wide load range are achieved using all Si devices.

14 SOLAR ENERGY↗
DOE OSTI2025

A Two-Stage Current Limiting Control Strategy for Direct-Droop-Controlled Grid-Forming Inverters

This paper presents a two-stage current limiting control strategy with fault ride-through capability for the direct-droop-controlled grid-forming (GFM) inverters. The proposed approach comprises Stage 1 and Stage 2 current limiting controls. During faults, Stage 1 current limiting control instantly clamps the inverter output current magnitude to its maximum transient limit by blocking the switching pulses to the insulated-gate bipolar transistors (IGBTs) with the help of a hysteresis loop control, and Stage 2 current limiting control limits the inverter output current magnitude to its steady-state limit by regulating the amplitude and frequency of the modulating waveform utilizing the active and reactive current limiting control loops. By implementing the current limiting actions in two stages, this approach can effectively limit the over-current within a few cycles after the fault occurrence and ensure synchronism to the grid after long-term fault events. The efficacy of the proposed control approach is validated through electromagnetic transient (EMT) simulation results conducted on a single GFM inverter-based test system and the IEEE 39-bus test system with multiple GFM inverters in the PSCAD platform.

Mohiuddin, Sheik Mohammad↗
DOE OSTI2020

A Generic Multivector Model Predictive Control With Symmetric Pulse Pattern for Hybrid Multilevel Converters

This article presents a generic multivector model predictive control (MV-MPC) method that has the potential to be applied to all hybrid multilevel converters (HMCs). It first locates the reference voltage vector in the 120° oblique coordinate to select the three adjacent voltage vectors to be applied over one control cycle. Then, the current tracking is guaranteed through duty cycle optimization and dc capacitor voltages are balanced by evaluating possible switching sequences that belong to the voltage vectors with optimal duty cycles. At last, the optimal switching sequence with a symmetric five- or seven-segment pulse pattern is generated using an external modulator. Here, the proposed generic MV-MPC can significantly improve the quality of the output current, while achieving a constant equivalent switching frequency at the same time. Experimental studies on an all silicon carbide HMC prototype, i.e., an active neutral point clamped converter with cascaded H-bridge, are presented to validate the effectiveness of the proposed MV-MPC strategy.

42 ENGINEERING↗
DOE OSTI2020

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. Furthermore, these results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

42 ENGINEERING↗
DOE OSTI2021

A Bulk-Capacitance Reduction Method Using Self-Driven Thyristor for AC-DC Converters

Universal serial bus power delivery (USB-PD) fast chargers equipped with wide-bandgap devices are driven to higher power density and efficiency. Furthermore, the indispensable high-voltage bulk capacitors used to smooth the rectifier output could take 40% of the total system volume due to the large capacitance value required. This paper discussed a capacitor reduction method using a self-driven thyristor scheme comprised of only three components in total. No extra control circuit is needed. Circuit analysis and design equations are presented, and the design results are implemented in a 60-W GaN-based active-clamp flyback converter. The measurement results on the prototype show a 36.4% reduction of the bulk-capacitor size with similar efficiency compared to the conventional solution.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2022

Vulnerability of a VOC-Based Inverter Due to Noise Injection and Its Mitigation

Even though virtual oscillator control (VOC)-based inverters do not communicate with each other, they need to make local measurements for control. The impact of tampering with these measured or sensed signals on the performance of a VOC-based inverter and synchronization of multiple such inverters is an important but open-ended issue. As such, this letter explores the impact of intentional side-channel noise intrusion (SNI) on the synchronization of VOC-based communication-free self-synchronizing inverters (CFSIs). Two different scenarios are investigated via experimental and analytical studies using a half-bridge neutral point clamped (NPC) single-phase CFSI. Furthermore, they address the impact of SNI on the ability of a CFSI to ensure a stable 60-Hz limit cycle and on the parallel operation of two such CFSIs to ensure synchronism to a common 60-Hz load frequency.

42 ENGINEERING↗