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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Photovoltaic system grounding and fault protection

The grounding and fault protection aspects of large photovoltaic power systems are studied. Broadly, the overlapping functions of these two plant subsystems include providing for the safety of personnel and equipment. Grounding subsystem design is generaly governed by considerations of personnel safety and the limiting of hazardous voltages to which they are exposed during the occurrence of a fault or other misoperation of equipment. A ground system is designed to provide a safe path for fault currents. Metal portions of the modules, array structures, and array foundations are used as a part of the ground system, provided that they and their interconnection are designed to be suitably reliable over the life of the plant. Several alternative types of fault protection and detection equipment are designed into the source circuits and dc buses feeding the input terminals of the subfield power conditioner. This design process requires evaluation of plausible faults, equipment, and remedial actions planned to correct faults. The evaluation should also consider life cycle cost impacts.

Stolte, W. J.↗
NASA NTRS1992

HDL to verification logic translator

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

Gambles, J. W.↗
NASA NTRS1995

Accelerometer having integral fault null

An improved accelerometer is introduced. It comprises a transducer responsive to vibration in machinery which produces an electrical signal related to the magnitude and frequency of the vibration; and a decoding circuit responsive to the transducer signal which produces a first fault signal to produce a second fault signal in which ground shift effects are nullified.

Bozeman, Richard J., Jr.↗
NASA NTRS1983

Electrical safety for high voltage arrays

A number of key electrical safety requirements for the high voltage arrays of central station photovoltaic power systems are explored. The suitability of representative industrial DC power switchgear for control and fault protection was evaluated. Included were AC/DC circuit breakers, electromechanical contactors and relays, load interruptors, cold disconnect devices, sectionalizing switches, and high voltage DC fuses. As appropriate, steady state and transient characteristics were analyzed. Failure modes impacting upon operation and maintenance safety were also identified, as were the voltage withstand and current interruption levels.

Marshall, N. A.↗
NASA NTRS2021

NASA Engineering and Safety Center Technical Bulletin No. 19-01-1: Mitigating Risks of Single-Event Effects in Space Applications

Since most Electrical, Electronic, and Electromechanical (EEE) parts are intended for terrestrial applications, they are susceptible to a range of radiation threats in the space environment if the resulting effects are not properly characterized and mitigated. Even specially designed radiation-hardened parts may not be tolerant to all types of radiation effects. Radiation hardness is a multi-dimensional property of any part that describes intrinsic abilities to tolerate various radiation environments [1,2]. Effects to be concerned with include total ionizing dose, total non-ionizing dose, and single-event effects (SEE) – all of which depend on the mission, environment, application, and lifetime. Radiation effects concerns may be the same whether a EEE part is Commercial-Off-The-Shelf (COTS), MIL-SPEC, or some other variant, all of which are susceptible to the same radiation threats [3]. SEE consequences range from recoverable faults to catastrophic failure. Like other random faults, SEE can be mitigated with informed circuit design practices at the device, card, and/or system level.

Single-event effects↗
NASA NTRS1972

Redundancy approaches in bubble domain memories

Fabrication of integrated circuit chips to compensate for faulty memory elements is discussed. Procedure for testing chips to determine extent of redundancy and faults is described. Mathematical model to define operation is presented. Schematic circuit diagram of test equipment is provided.

Almasi, G. S.↗
NASA NTRS1993

Self-checking sequential circuit design using m-out-of-n codes

A technique for designing sequential circuits which are totally self-checking for single stuck at faults is presented. This technique uses m-out-of-n codes for state assignments and for output encoding. The next stage logic and the output logic are implemented such that any stuck-at-fault will either create a single bit error or unidirectional multibit error at the output. The technique has been applied to MCNC benchmark circuits and the overhead is estimated.

Busaba, F. Y.↗
NASA NTRS1997

Test Report - Fault Current Through Graphite Filament Reinforced Plastic

Tests were performed to determine the damage to samples of composite material when a current carrying wire is shorted to the surface of the composite material, and to determine whether enough current can flow through the material to blow a fuse before damage can occur. Fault current tests were performed on samples of graphite epoxy materials. Samples consisted of six layers of IM7 graphite fiber mat in Hercules 8552 epoxy resin. A variable power supply provided up to 35 amps of current. The high voltage side of the power supply was attached to a wire at the end of a hinged arm, and the low side was attached to the edge of the sample. To test joints, the return was connected to the edge of one sample, and the high side was shorted to the top of the other sample. Tests show that when current exceeds approximately 5 amps, the graphite glows, and the epoxy melts out at the shorted contact. At higher current levels the epoxy burns. At voltages above 15 volts the epoxy outer coat is easily broken, and fire, flame, and a rise in current occur suddenly. When joints are introduced, resistance is increased, and the maximum current resulting from a short circuit to the graphite epoxy is reduced. This condition can easily result in fault current lower than the circuit breaker limit and higher than the 5 amp ignition level. The shorting contact and the joint become hot spots with melting epoxy, smoke, and fire.

Evans, R. W.↗
NASA NTRS1990

Efficient design of CMOS TSC checkers

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

Biddappa, Anita↗
NASA NTRS1990

Generating Weighted Test Patterns for VLSI Chips

Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

Siavoshi, Fardad↗
NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗
NASA NTRS1974

Design analysis and computer-aided performance evaluation of shuttle orbiter electrical power system. Volume 1: Summary

Studies were conducted to develop appropriate space shuttle electrical power distribution and control (EPDC) subsystem simulation models and to apply the computer simulations to systems analysis of the EPDC. A previously developed software program (SYSTID) was adapted for this purpose. The following objectives were attained: (1) significant enhancement of the SYSTID time domain simulation software, (2) generation of functionally useful shuttle EPDC element models, and (3) illustrative simulation results in the analysis of EPDC performance, under the conditions of fault, current pulse injection due to lightning, and circuit protection sizing and reaction times.

Source record↗
NASA NTRS2008

Instrumentation System Diagnoses a Thermocouple

An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.

Perotti, Jose↗
NASA NTRS1992

A set-associative, fault-tolerant cache design

The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.

Lamet, Dan↗
NASA NTRS2009

Methods for Probabilistic Fault Diagnosis: An Electrical Power System Case Study

Health management systems that more accurately and quickly diagnose faults that may occur in different technical systems on-board a vehicle will play a key role in the success of future NASA missions. We discuss in this paper the diagnosis of abrupt continuous (or parametric) faults within the context of probabilistic graphical models, more specifically Bayesian networks that are compiled to arithmetic circuits. This paper extends our previous research, within the same probabilistic setting, on diagnosis of abrupt discrete faults. Our approach and diagnostic algorithm ProDiagnose are domain-independent; however we use an electrical power system testbed called ADAPT as a case study. In one set of ADAPT experiments, performed as part of the 2009 Diagnostic Challenge, our system turned out to have the best performance among all competitors. In a second set of experiments, we show how we have recently further significantly improved the performance of the probabilistic model of ADAPT. While these experiments are obtained for an electrical power system testbed, we believe they can easily be transitioned to real-world systems, thus promising to increase the success of future NASA missions.

Ricks, Brian W.↗
NASA NTRS1978

A study of standard building blocks for the design of fault-tolerant distributed computer systems

This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.

Rennels, D. A.↗
NASA NTRS1989

Cascaded resonant bridge converters

A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.

Stuart, Thomas A.↗
NASA NTRS1987

Ferroresonant flux coupled battery charger

A battery charger for incorporation into an electric-powered vehicle is disclosed. The charger includes a ferroresonant voltage-regulating circuit for providing an output voltage proportional to the frequency of an input AC voltage. A high frequency converter converts a DC voltage supplied, for example, from a rectifier connected to a standard AC outlet, to a controlled frequency AC voltage which is supplied to the input of the ferroresonant circuit. The ferroresonant circuit includes an output, a saturable core transformer connected across the output, and a first linear inductor and a capacitor connected in series across the saturable core transformer and tuned to resonate at the third harmonic of the AC voltage from the high frequency converter. The ferroresonant circuit further includes a second linear inductor connected between the input of the ferroresonant circuit and the saturable core transformer. The output voltage from the ferroresonant circuit is rectified and applied across a pair of output terminals adapted to be connected to the battery to be charged. A feedback circuit compares the voltage across the output terminals with a reference voltage and controls the frequency of the AC voltage produced by the high frequency converter to maintain the voltage across the output terminals at a predetermined value. The second linear inductor provides a highly reactive load in the event of a fault across the output terminals to render the charger short-circuit proof.

McLyman, Colonel W. T.↗