Computer in the Loop: A Paradigm for Software Augmentation of Terrestrial Medical Support in Asynchronous Communication Environments
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Dana Levin↗
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Results for “asynchronous”
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Probabilistic Processing of Asynchronous Geiger-Mode Avalanche Photodiode Arrays for Background Rate Measurements
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Duerr, Erik↗
Multiband study of RX J0838−2827 and XMM J083850.4−282759: a new asynchronous magnetic cataclysmic variable and a candidate transitional millisecond pulsar
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N. Rea↗
Digital Synchronizer without Metastability
A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.
Simle, Robert M.↗
Computational chaos in massively parallel neural networks
A fundamental issue which directly impacts the scalability of current theoretical neural network models to massively parallel embodiments, in both software as well as hardware, is the inherent and unavoidable concurrent asynchronicity of emerging fine-grained computational ensembles and the possible emergence of chaotic manifestations. Previous analyses attributed dynamical instability to the topology of the interconnection matrix, to parasitic components or to propagation delays. However, researchers have observed the existence of emergent computational chaos in a concurrently asynchronous framework, independent of the network topology. Researcher present a methodology enabling the effective asynchronous operation of large-scale neural networks. Necessary and sufficient conditions guaranteeing concurrent asynchronous convergence are established in terms of contracting operators. Lyapunov exponents are computed formally to characterize the underlying nonlinear dynamics. Simulation results are presented to illustrate network convergence to the correct results, even in the presence of large delays.
Barhen, Jacob↗
RAID 7 disk array
Each RAID level reflects a different design architecture. Associated with each is a backdrop of imposed limitations, as well as possibilities which may be exploited within the architectural constraints of that level. There are three unique features that differentiate RAID 7 from all other levels. RAID 7 is asynchronous with respect to usage of I/O data paths. Each I/O drive (includes all data and one parity drives) as well as each host interface (there may be multiple host interfaces) has independent control and data paths. This means that each can be accessed completely, independently, of the other. This is facilitated by a separate device cache for each device/interface as well. RAID 7 is asynchronous with respect to device hierarchy and data bus utilization. Each drive and each interface is connected to a high speed data bus controlled by the embedded operating system to make independent transfers to and from central cache. RAID 7 is asynchronous with respect to the operation of an embedded real time process oriented operating system. This means that exclusive and independent of the host, or multiple host paths, the embedded OS manages all I/O transfers asynchronously across the data and parity drives. A key factor to consider is that of the RAID 7's ability to anticipate and match host I/O usage patterns. This yields the following benefits over RAID's built around micro-code based architectures. RAID 7 appears to the host as a normally connected Big Fast Disk (BFD). RAID 7 appears, from the perspective of the individual disk devices, to minimize the total number of accesses and optimize read/write transfer requests. RAID 7 smoothly integrates the random demands of independent users with the principles of spatial and temporal locality. This optimizes small, large, and time sequenced I/O requests which results in users having an I/O performance which approaches performance to that of main memory.
Stout, Lloyd↗
Control strategy for a variable-speed wind energy conversion system
A control concept for a variable-speed wind energy conversion system is proposed, for which a self-exited asynchronous cage generator is used along with a system of thyristor converters. The control loops are the following: (1) regulation of the entrainment speed as function of available mechanical energy by acting on the resistance couple of the asynchronous generator; (2) control of electric power delivered to the asynchronous machine, functioning as a motor, for start-up of the vertical axis wind converter; and (3) limitation of the slip value, and by consequence, of the induction currents in the presence of sudden variations of input parameters.
Jacob, A.↗
Fairness of channel access for non-time-critical traffic using the FDDI token ring protocol
The Fiber Distributed Data Interface (FDDI) is an ANSI draft proposed standard for a 100 megabit per second fiber optic token ring. FDDI supports two types of traffic, synchronous and asynchronous. Synchronous traffic is time critical traffic; stations are assigned guaranteed bandwidth to support their synchronous needs. Asynchronous traffic is lower priority and is sent only if time permits. It is proved analytically that the FDDI access protocol provides all stations on the ring with equal access to the channel to transmit asynchronous frames, regardless of the relative sizes of synchronous bandwidth allocations for individual stations. Analytic results are supported with data from simulation runs.
Johnson, M. J.↗
Throughput analysis of the IEEE 802.4 token bus standard under heavy load
It has become clear in the last few years that there is a trend towards integrated digital services. Parallel to the development of public Integrated Services Digital Network (ISDN) is service integration in the local area (e.g., a campus, a building, an aircraft). The types of services to be integrated depend very much on the specific local environment. However, applications tend to generate data traffic belonging to one of two classes. According to IEEE 802.4 terminology, the first major class of traffic is termed synchronous, such as packetized voice and data generated from other applications with real-time constraints, and the second class is called asynchronous which includes most computer data traffic such as file transfer or facsimile. The IEEE 802.4 token bus protocol which was designed to support both synchronous and asynchronous traffic is examined. The protocol is basically a timer-controlled token bus access scheme. By a suitable choice of the design parameters, it can be shown that access delay is bounded for synchronous traffic. As well, the bandwidth allocated to asynchronous traffic can be controlled. A throughput analysis of the protocol under heavy load with constant channel occupation of synchronous traffic and constant token-passing times is presented.
Pang, Joseph↗
Compression of digital images over local area networks. Appendix 1: Item 3
Differential Pulse Code Modulation (DPCM) has been used with speech for many years. It has not been as successful for images because of poor edge performance. The only corruption in DPC is quantizer error but this corruption becomes quite large in the region of an edge because of the abrupt changes in the statistics of the signal. We introduce two improved DPCM schemes; Edge correcting DPCM and Edge Preservation Differential Coding. These two coding schemes will detect the edges and take action to correct them. In an Edge Correcting scheme, the quantizer error for an edge is encoded using a recursive quantizer with entropy coding and sent to the receiver as side information. In an Edge Preserving scheme, when the quantizer input falls in the overload region, the quantizer error is encoded and sent to the receiver repeatedly until the quantizer input falls in the inner levels. Therefore these coding schemes increase the bit rate in the region of an edge and require variable rate channels. We implement these two variable rate coding schemes on a token wing network. Timed token protocol supports two classes of messages; asynchronous and synchronous. The synchronous class provides a pre-allocated bandwidth and guaranteed response time. The remaining bandwidth is dynamically allocated to the asynchronous class. The Edge Correcting DPCM is simulated by considering the edge information under the asynchronous class. For the simulation of the Edge Preserving scheme, the amount of information sent each time is fixed, but the length of the packet or the bit rate for that packet is chosen depending on the availability capacity. The performance of the network, and the performance of the image coding algorithms, is studied.
Gorjala, Bhargavi↗
High performance interconnection between high data rate networks
The bridge/gateway system needed to interconnect a wide range of computer networks to support a wide range of user quality-of-service requirements is discussed. The bridge/gateway must handle a wide range of message types including synchronous and asynchronous traffic, large, bursty messages, short, self-contained messages, time critical messages, etc. It is shown that messages can be classified into three basic classes, synchronous and large and small asynchronous messages. The first two require call setup so that packet identification, buffer handling, etc. can be supported in the bridge/gateway. Identification enables resequences in packet size. The third class is for messages which do not require call setup. Resequencing hardware based to handle two types of resequencing problems is presented. The first is for a virtual parallel circuit which can scramble channel bytes. The second system is effective in handling both synchronous and asynchronous traffic between networks with highly differing packet sizes and data rates. The two other major needs for the bridge/gateway are congestion and error control. A dynamic, lossless congestion control scheme which can easily support effective error correction is presented. Results indicate that the congestion control scheme provides close to optimal capacity under congested conditions. Under conditions where error may develop due to intervening networks which are not lossless, intermediate error recovery and correction takes 1/3 less time than equivalent end-to-end error correction under similar conditions.
Foudriat, E. C.↗
Adaptive digital beamforming for a CDMA mobile communications payload
In recent years, Spread-Spectrum Code Division Multiple Access (CDMA) has become a very popular access scheme for mobile communications due to a variety of reasons: excellent performance in multipath environments, high scope for frequency reuse, graceful degradation near saturation, etc. In this way, a CDMA system can support simultaneous digital communication among a large community of relatively uncoordinated users sharing a given frequency band. Nevertheless, there are also important problems associated with the use of CDMA. First, in a conventional CDMA scheme, the signature sequences of asynchronous users are not orthogonal and, as the number of active users increases, the self-noise generated by the mutual interference between users considerably degrades the performance, particularly in the return link. Furthermore, when there is a large disparity in received powers - due to differences in slant range or atmospheric attenuation - the non-zero cross-correlation between the signals gives rise to the so-called near-far problem. This leads to an inefficient utilization of the satellite resources and, consequently, to a drastic reduction in capacity. Several techniques were proposed to overcome this problem, such as Synchronized CDMA - in which the signature sequences of the different users are quasi-orthogonal - and power control. At the expense of increased network complexity and user coordination, these techniques enable the system capacity to be restored by equitably sharing the satellite resources among the users. An alternative solution is presented based upon the use of time-reference adaptive digital beamforming on board the satellite. This technique enables a high number of independently steered beams to be generated from a single phased array antenna, which automatically track the desired user signal and null the unwanted interference source. In order to use a time-reference adaptive antenna in a communications system, the main challenge is to obtain a reference signal highly correlated with the desired user signal and uncorrelated with the interferences. CDMA lends itself very easily to the generation of such a reference signal, thanks to the a priori knowledge of the user's signature sequence. First, the integration of an adaptive antenna in an asynchronous CDMA system is analyzed. The adaptive antenna system can provide increased interference rejection - much higher than that afforded by the code alone - and, since CDMA is mainly interference limited, any reduction in interference converts directly and linearly into an increase in capacity. Analyses and computer simulations are presented that show how an asynchronous CDMA system incorporating adaptive beamforming can provide at least as much capacity as a synchronous system. More importantly, the proposed concept allows the near-far effect to be mitigated without requiring a tight coordination of the users in terms of transmitted power control or network synchronization. The system is extremely robust to the near-far effect because the signals reaching the satellite from directions other than that of the desired user - which are likely to have different power levels - are adaptively canceled by the antenna. Finally, a payload architecture is presented that illustrates the practical implementation of this concept. This digital payload architecture demonstrates that with the advent of high performance CMOS digital processing, the on-board implementation of complex DSP techniques - in particular Digital Beamforming - has become possible, being most attractive for Mobile Satellite Communications.
Munoz-Garcia, Samuel G.↗
Modeling and Analysis of Mixed Synchronous/Asynchronous Systems
Practical safety-critical distributed systems must integrate safety critical and non-critical data in a common platform. Safety critical systems almost always consist of isochronous components that have synchronous or asynchronous interface with other components. Many of these systems also support a mix of synchronous and asynchronous interfaces. This report presents a study on the modeling and analysis of asynchronous, synchronous, and mixed synchronous/asynchronous systems. We build on the SAE Architecture Analysis and Design Language (AADL) to capture architectures for analysis. We present preliminary work targeted to capture mixed low- and high-criticality data, as well as real-time properties in a common Model of Computation (MoC). An abstract, but representative, test specimen system was created as the system to be modeled.
Driscoll, Kevin R.↗
A synchronous binary array divider
An asynchronous binary divider formed of an array of identical logic cells is described. Each cell includes a single bit binary subtractor and a selection gate. The array is connected to divisor, dividend, quotient and remainder registers. Divisor and dividend numbers are read into the divisor and dividend registers, respectively. The array of identical logic cells performs the division in parallel asynchronously and places the results of the division in the quotient and remainder registers for subsequent readout.
Wang, G. Y.↗
RAMP: A fault tolerant distributed microcomputer structure for aircraft navigation and control
RAMP consists of distributed sets of parallel computers partioned on the basis of software and packaging constraints. To minimize hardware and software complexity, the processors operate asynchronously. It was shown that through the design of asymptotically stable control laws, data errors due to the asynchronism were minimized. It was further shown that by designing control laws with this property and making minor hardware modifications to the RAMP modules, the system became inherently tolerant to intermittent faults. A laboratory version of RAMP was constructed and is described in the paper along with the experimental results.
Dunn, W. R.↗
RAMP - A fault tolerant distributed microcomputer structure for aircraft navigation and control
Design methodologies for realizing future high authority autoflight control systems are being investigated, taking into account also the study of distributed microcomputer architectures. Attention is given to the redundant asynchronous microprocessor (RAMP) structure. RAMP comprises a connected network of microcomputers which has as input command and sensor information, and which generates servo information to drive actuators, and thrust linkages. Tolerance to hardware failures is achieved by static redundancy. Results of a failed microcomputer are simply rejected. This is done in lieu of dynamic redundancy wherein the distributed computer system performs real time fault detection and reconfiguration of the system. Attention is given to the RAMP network structure and operation, flight control with parallel asynchronous computers, and intermittent fault tolerance.
Dunn, W. R.↗
Analysis of backward error recovery for concurrent processes with recovery blocks
Three different methods of implementing recovery blocks (RB's). These are the asynchronous, synchronous, and the pseudo recovery point implementations. Pseudo recovery points so that unbounded rollback may be avoided while maintaining process autonomy are proposed. Probabilistic models for analyzing these three methods under standard assumptions in computer performance analysis, i.e., exponential distributions for related random variables were developed. The interval between two successive recovery lines for asynchronous RB's mean loss in computation power for the synchronized method, and additional overhead and rollback distance in case PRP's are used were estimated.
Shin, K. G.↗
Synchronization of magnetic stars in binary systems
Asynchronous rotation of magnetic stars in close binary systems drives substantial field-aligned electrical currents between the magnetic star and its companion. The resulting magnetohydrodynamic torque is able to account for the heretofore unexplained synchronous rotation of the strongly magnetic degenerate dwarf component in systems like AM Her, VV Pup, AN UMa, and EF Eri as well as the magnetic A type component in systems like HD 98088 and 41 Tauri. The electric fields produced by even a small asynchronism are large and may accelerate some electrons to high energies, producing radio emission. The total energy dissipation rate in systems with degenerate dwarf spin periods as short as 1 minute may reach 10 to the 33rd ergs/s. Total luminosities of this order may be a characteristic feature of such systems.
Lamb, F. K.↗