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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1999

Advanced Microelectronics Technologies for Future Small Satellite Systems

Future small satellite systems for both Earth observation as well as deep-space exploration are greatly enabled by the technological advances in deep sub-micron microelectronics technologies. Whereas these technological advances are being fueled by the commercial (non-space) industries, more recently there has been an exciting new synergism evolving between the two otherwise disjointed markets. In other words, both the commercial and space industries are enabled by advances in low-power, highly integrated, miniaturized (low-volume), lightweight, and reliable real-time embedded systems. Recent announcements by commercial semiconductor manufacturers to introduce Silicon On Insulator (SOI) technology into their commercial product lines is driven by the need for high-performance low-power integrated devices. Moreover, SOI has been the technology of choice for many space semiconductor manufacturers where radiation requirements are critical. This technology has inherent radiation latch-up immunity built into the process, which makes it very attractive to space applications. In this paper, we describe the advanced microelectronics and avionics technologies under development by NASA's Deep Space Systems Technology Program (also known as X2000). These technologies are of significant benefit to both the commercial satellite as well as the deep-space and Earth orbiting science missions. Such a synergistic technology roadmap may truly enable quick turn-around, low-cost, and highly capable small satellite systems for both Earth observation as well as deep-space missions.

Alkalai, Leon↗
NASA NTRS2001

A Library of Rad Hard Mixed-Voltage/Mixed-Signal Building Blocks for Integration of Avionics Systems for Deep Space

To build the sensor intensive system-on-a-chip for the next generation spacecrafts for deep space, Center for Integration of Space Microsystems at JPL (CISM) takes advantage of the lower power rating and inherent radiation resistance of Silicon on Insulator technology (SOI). We are developing a suite of mixed-voltage and mixed-signal building blocks in Honeywell's SOI process that can enable the rapid integration of the next generation avionics systems with lower power rating, higher reliability, longer life, and enhanced radiation tolerance for spacecrafts such as the Europa Orbiter and Europa Lander. The mixed-voltage building blocks are predominantly for design of adaptive power management systems. Their design centers around an LDMOS structure that is being developed by Honeywell, Boeing Corp, and the University of Idaho. The mixed-signal building blocks are designed to meet the low power, extreme radiation requirement of deep space applications. These building blocks are predominantly used to interface analog sensors to the digital CPU of the next generation avionics system on a chip. Additional information is contained in the original extended abstract.

Mojarradi, M. M.↗
NASA NTRS2001

Electronics for Extreme Environments

Most of the NASA missions involve extreme environments comprising radiation and low or high temperatures. Current practice of providing friendly ambient operating environment to electronics costs considerable power and mass (for shielding). Immediate missions such as the Europa orbiter and lander and Mars landers require the electronics to perform reliably in extreme conditions during the most critical part of the mission. Some other missions planned in the future also involve substantial surface activity in terms of measurements, sample collection, penetration through ice and crust and the analysis of samples. Thus it is extremely critical to develop electronics that could reliably operate under extreme space environments. Silicon On Insulator (SOI) technology is an extremely attractive candidate for NASA's future low power and high speed electronic systems because it offers increased transconductance, decreased sub-threshold slope, reduced short channel effects, elimination of kink effect, enhanced low field mobility, and immunity from radiation induced latch-up. A common belief that semiconductor devices function better at low temperatures is generally true for bulk devices but it does not hold true for deep sub-micron SOI CMOS devices with microscopic device features of 0.25 micrometers and smaller. Various temperature sensitive device parameters and device characteristics have recently been reported in the literature. Behavior of state of the art technology devices under such conditions needs to be evaluated in order to determine possible modifications in the device design for better performance and survivability under extreme environments. Here, we present a unique approach of developing electronics for extreme environments to benefit future NASA missions as described above. This will also benefit other long transit/life time missions such as the solar sail and planetary outposts in which electronics is out open in the unshielded space at the ambient space temperatures and always exposed to radiation. Additional information is contained in the original extended abstract.

Patel, J. U.↗
NASA NTRS2003

Low-Power SOI CMOS Transceiver

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Fujikawa, Gene↗
NASA NTRS2003

Power Electronics Being Developed for Deep Space Cryogenic Applications

Electronic circuits and systems designed for deep space missions need to operate reliably and efficiently in harsh environments that include very low temperatures. Spacecraft that operate in such cold environments carry a large number of heaters so that the ambient temperature for the onboard electronics remains near 20 C. Electronics that can operate at cryogenic temperatures will simplify system design and reduce system size and weight by eliminating the heaters and their associated structures. As a result, system development and launch cost will be reduced. At the NASA Glenn Research Center, an ongoing program is focusing on the development of power electronics geared for deep space low-temperature environments. The research and development efforts include electrical components design, circuit design and construction, and system integration and demonstration at cryogenic temperatures. Investigations are being carried out on circuits and systems that are targeted for use in NASA missions where low temperatures will be encountered: devices such as ceramic and tantalum capacitors, metal film resistors, semiconductor switches, magnetics, and integrated circuits including dc/dc converters, operational amplifiers, voltage references, and motor controllers. Test activities cover a wide range of device and circuit performance under simple as well as complex test conditions, such as multistress and thermal cycling. The effect of low-temperature conditions on the switching characteristics of an advanced silicon-on-insulator field effect transistor is shown. For gate voltages (VGS) below 2.6 V, drain currents at -190 C are lower than drain currents at room temperature (20 C).

Patterson, Richard L.↗
NASA NTRS2005

PDSOI and Radiation Effects: An Overview

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

Forgione, Joshua B.↗
NASA NTRS2006

Large format imaging arrays for the Atacama Cosmology Telescope

We describe progress in the fabrication, characterization, and production of detector arrays for the Atacama Cosmology Telescope (ACT). The completed ACT instrument is specified to image simultaneously at 145, 225, and 265 GHz using three 32x32 filled arrays of superconducting transition edge sensors (TES) read out with time-division-multiplexed SQUID amplifiers. We present details of the pixel design and testing including the optimization of the electrical parameters for multiplexed readout. Using geometric noise suppression and careful tuning of operation temperature and device bias resistance, the excess noise in the TES devices is balanced with detector speed for interfacing with the ACT optics. The design also accounts for practical tolerances such as transition temperature gradients and scatter that occur in the production of multiple wafers to populate fully the kilopixel cameras. We have developed an implanted absorber layer compatible with our silicon-on-insulator process that allows for tunable optical resistance with requisite on-wafer uniformity and wafer-to-wafer reproducibility. Arrays of 32 elements have been tested in the laboratory environment including electrical, optical, and multiplexed performance. Given this pixel design, optical tests and modeling are used to predict the performance of the filled array under anticipated viewing conditions. Integration of the filled array of pixels with a tuned backshort and dielectric plate in front of the array maximize absorption and the focal plane and suppress reflections. A mechanical design for the build of the full structure is completed and we report on progress toward the construction of a prototype array for first light on the ACT.

Chervenak, J. A.↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗
NASA NTRS2002

Complemenary body driving - a low voltage analog circuit technique for SOI

This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV; and a rail-to-rail, constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35~1 partially-depleted Silicon-on-Insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.

neuro-prosthetic devices cortical signals↗
NASA NTRS2007

Interpretation of TEPC Measurements in Space Flights for Radiation Monitoring

For the proper interpretation of radiation data measured in space, the results of integrated radiation transport models were compared with the tissue equivalent proportional counter (TEPC) measurements. TEPC is a simple, time-dependent approach to radiation monitoring for astronauts on board the International Space Station. Another and a newer approach to microdosimetry is the use of silicon-on-insulator (SOI) technology launched on the MidSTAR-1 mission in low Earth orbit (LEO). In the radiation protection practice, the average quality factor of a radiation field is defined as a function of linear energy transfer (LET), Qave(LET). However, TEPC measures the average quality factor as a function of the lineal energy y, Qave(y), defined as the average energy deposition in a volume divided by the average chord length of the volume. The deviation of y from LET is caused by energy straggling, delta-ray escape or entry, and nuclear fragments produced in the detector volume. The response distribution functions of the wall-less and walled TEPCs were calculated from Monte-Carlo track simulations. Using an integrated space radiation model (which includes the transport codes HZETRN and BRYNTRN, and the quantum nuclear interaction model QMSFRG) and the resultant response distribution functions from Monte-Carlo track simulations, we compared model calculations with the walled-TEPC measurements from NASA missions in LEO and made predictions for the lunar and the Mars missions. Good agreement was found for Qave(y) between the model and measured spectra from past NASA missions. The Qave(y) values for the trapped or the solar protons ranged from 1.9-2.5. This over-estimates the Qave(LET) values which ranged from 1.4-1.6. Both quantities increase with shield thickness due to nuclear fragmentation. The Qave(LET) for the complete GCR spectra was found to be 3.5-4.5, while flight TEPCs measured 2.9-3.4 for Qave(y). The GCR values are decreasing with the shield thickness. Our analysis of the measurements of TEPCs can be used for a proper interpretation of observed data of monitoring the space radiation environment.

Kim, Myung-Hee Y.↗
NASA NTRS2007

Comparison of Integrated Radiation Transport Models with TEPC Measurements for the Average Quality Factors in Spaceflights

The purpose of this work is to test our theoretical model for the interpretation of radiation data measured in space. During the space missions astronauts are exposed to the complex field of radiation type and kinetic energies from galactic cosmic rays (GCR), trapped protons, and sometimes solar particle events (SPEs). The tissue equivalent proportional counter (TEPC) is a simple time-dependent approach for radiation monitoring for astronauts on board the International Space Station. Another and a newer approach to Microdosimetry is the use of silicon-on-insulator (SOI) technology launched on the MidSTAR-1 mission in low Earth orbit (LEO). In the radiation protection practice, the average quality factor of a radiation field is defined as a function of linear energy transfer (LET), Q(sub ave)(LET). However, TEPC measures the average quality factor as a function of the lineal energy y, Q(sub ave)(y), defined as the average energy deposition in a volume divided by the average chord length of the volume. Lineal energy, y, deviates from LET due to energy straggling, delta-ray escape or entry, and nuclear fragments produced in the detector volume. Monte Carlo track structure simulation was employed to obtain the response of a TEPC irradiated with charged particle for an equivalent site diameter of 1 micron of wall-less counter. The calculated data of the energy absorption in the wall-less counter were compiled for various y values for several ion types at various discrete projectile energy levels. For the simulation of TEPC response from the mixed radiation environments inside a spacecraft, such as, Space Shuttle and International Space Station, the complete microdosimetric TEPC response, f( y, E, Z), were calculated with the Monte Carlo theoretical results by using the first order Lagrangian interpolation for a monovariate function at a given y value (y = 0.1 keV/micron 5000 keV/micron) at any projectile energy level (E = 0.01 MeV/u to 50,000 MeV/u) of each specific radiation type (Z = 1 to 28). Because the anomalous response has been observed at large event sizes in the experiment due to the escape of energy out of sensitive volume by delta-rays and the entry of delta-rays from the high-density wall into the low-density gas-volume cavity, Monte Carlo simulation was also made for the response of a walled-TEPC with wall thickness 2 mm and density 1 g/cm(exp 3). The radius of cavity was set to 6.35 mm and a gas density 7.874 x 10(exp -5) g/cm(exp 3). The response of the walled- and the wall-less counters were compared. The average quality factor Q(sub ave)(y) for trapped protons on STS-89 demonstrated the good agreement between the model calculations and flight TEPC data as shown. Using an integrated space radiation model (this includes the transport codes HZETRN and BRYNTRN, the quantum nuclear interaction model QMSFRG) and the resultant response distribution functions of walled-TEPC from Monte-Carlo track simulations, we compared model calculations with walled-TEPC measurements from NASA missions in LEO and made predictions for the lunar and the Mars missions. The Q(sub ave)(y) values for the trapped or the solar protons ranged from 1.9-2.5. This over-estimates the Qave(LET) values which ranged from 1.4-1.6. Both quantities increase with shield thickness due to nuclear fragmentation. The Q(sub ave)(LET) for the complete GCR spectra was found to be 3.5-4.5, while flight TEPCs measured 2.9-3.4 for Q(sub ave)(y). The GCR values are decreasing with the shield thickness. Our analysis for a proper interpretation of data supports the use of TEPCs for monitoring space radiation environment.

Kim, Myung-Hee Y.↗
NASA NTRS2006

The USNA MIDN Microdosimeter Instrument

This paper describes the MIcroDosimetry iNstrument (MIDN) mission now under development at the United States Naval Academy. The instrument is manifested to fly on the MidSTAR-1 spacecraft, which is the second spacecraft to be developed and launched by the Academy s faculty and midshipmen. Launch is scheduled for 1 September 2006 on an ATLAS-5 launch vehicle. MIDN is a rugged, portable, low power, low mass, solid-state microdosimeter designed to measure in real time the energy distributions of energy deposited by radiation in microscopic volumes. The MIDN microdosimeter sensor is a reverse-biased silicon p-n junction array in a Silicon-On-Insulator (SOI) configuration. Microdosimetric frequency distributions as a function of lineal energies determine the radiation quality factors in support of radiation risk estimation to humans.

Pisacane, V. L.↗
NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗
NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗
NASA NTRS2009

SOI CMOS Imager with Suppression of Cross-Talk

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗