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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
The JPL-led CSP Consortium of enterprises representing government agencies and private companies has jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Effect of gold plating on soldered connections
High permeability semiconductor used for close- tolerance soldering by concentration of energy of magnetic field
A Solder Committee designated to investigate a solder cracking phenomena occurring on the SATURN electrical/electronic hardware found the cause to be induced stress in the soldered connections rather than faulty soldering techniques. The design of the printed circuit (PC) board assemblies did not allow for thermal expansion of the boards that occurred during normal operation. The difference between the thermal expansion properties of the boards and component lead materials caused stress and cracking in the soldered connections. The failure mechanism and various PC boards component mounting configurations are examined in this report. Effective rework techniques using flanged tubelets, copper tubelets, and soft copper wiring are detailed. Future design considerations to provide adequate strain relief in mounting configurations are included to ensure successful solder terminations.
Solar cell submodule fabrication and design for Mariner and Surveyor spacecraft, describing automatic conveyor soldering oven
Welding technique produces more reliable joints than soldering. Investigation used different sizes of copper conductors and component lead ribbons, corrosion protection platings, and melting points of metals being joined. Optimum combination is gold-plated component lead ribbons and solder-plated copper conductors.
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This paper discusses limitation of each system and provides representative inspection images for CCGA/BGA assemblies.
Inspection results along with SEM and optical cross-sectional photos revealing damage and failure mechanisms will also be presented.
The test results for numerous chip scale package assembly performed under MicrotypeBGA Consortium led by the Jet Propulsion Laboratory have been published previously.
System in a package (SIP) development is a response to an increasing demand for integration of different functions into one unit to reduce size and cost and improve functionality. Qualification of the newly developed multifunctional electronics are becoming complex at the package level and even more at the second and system levels.
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Explore the source record for details and available documents.
A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.
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A JPL-led chip scale package (CSP) Consortium of enterprises, composed of representing agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.