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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7

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NASA NTRS1976

Experimental investigation of a double-diffused MOS structure

Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS technology. A number of inverters connected as ring oscillators were used as a vehicle to test the performance and to verify the anticipated benefits. The propagation time-power dissipation product and process related parameters were measured and evaluated. This report includes (1) details of the process; (2) test data and design details for the DMOS transistor, the load device, the inverter, the ring oscillator, and a shift register with a novel tapered geometry for the output stages; and (3) an analytical treatment of the effect of the distributed silicon gate resistance and capacitance on the speed of DMOS transistors.

Lin, H. C.↗

NASA NTRS1976

Investigation of television transmission using adaptive delta modulation principles

The results are presented of a study on the use of the delta modulator as a digital encoder of television signals. The computer simulation of different delta modulators was studied in order to find a satisfactory delta modulator. After finding a suitable delta modulator algorithm via computer simulation, the results were analyzed and then implemented in hardware to study its ability to encode real time motion pictures from an NTSC format television camera. The effects of channel errors on the delta modulated video signal were tested along with several error correction algorithms via computer simulation. A very high speed delta modulator was built (out of ECL logic), incorporating the most promising of the correction schemes, so that it could be tested on real time motion pictures. Delta modulators were investigated which could achieve significant bandwidth reduction without regard to complexity or speed. The first scheme investigated was a real time frame to frame encoding scheme which required the assembly of fourteen, 131,000 bit long shift registers as well as a high speed delta modulator. The other schemes involved the computer simulation of two dimensional delta modulator algorithms.

Schilling, D. L.↗

NASA NTRS1976

A 128K-bit CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications.

Siemens, K. H.↗

NASA NTRS1975

Long frame sync words for binary PSK telemetry

Correlation criteria have previously been established for identifying whether a given binary sequence would be a good frame sync word for phase-shift keyed telemetry. In the past, the search for a good K-bit sync word has involved the application of these criteria to the entire set of 2 exponent K binary K-tuples. It is shown that restricting this search to a much smaller subset consisting of K-bit prefixes of pseudonoise sequences results in sync words of comparable quality, with greatly reduced computer search times for larger values of K. As an example, this procedure is used to find good sync words of length 16-63; from a storage viewpoint, each of these sequences can be generated by a 5- or 6-bit linear feedback shift register.

Levitt, B. K.↗

NASA NTRS1975

An efficient read-out system for multiwire proportional counter hodoscopes

An efficient scanning method for read-out of a multiwire proportional counter hodoscope is presented. This method which utilizes the grouping of wires in the hodoscope read-out system offers distinct advantages in speed and simplicity over systems employing long shift registers. Power consumption and cost can be minimized with this method because of slower clock speeds and a low parts count. This system has been constructed and used on a hodoscope for cosmic-ray trajectory measurements and a lower-power version has been designed for satellite applications.

Austin, R. W.↗

NASA NTRS1979

Simple digital pulse-programing circuit

Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.

Langston, J. L.↗

NASA NTRS1979

Data reformatting with less hardware

Dual-function integrated circuits use one shift register array instead of two to feed video data to seven tape channels thereby making system more reliable and less expensive than predecessor. Basic principle of reformatter is also applicable to multiplexing and frequency conversion circuits.

Engel, A.↗

NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗

NASA NTRS1978

A packet telemetry system employing ARQ error control

A proposed packet telemetry system employing automatic retransmission request (ARQ) mode of error control is characterized. Limitations of the present multiplexing/demultiplexing approach are considered, and the use of the proposed system in near-earth satellites in the 1980s is suggested. Onboard processing and an adaptive multiplexing technique are described, as is an elastic buffer, required because the instantaneous data rate will be different from the telemetry transmission rate. The telemetry packets would be encoded into a powerful error-detection block code. A mechanism involving temporary buffering in a long shift register will permit retransmission request from the ground station for packets received in error. The ARQ mode of operation should ensure essentially error-free transmission at lower signal-to-noise ratios and at considerably higher transmission rates than are usually used.

Greene, E. P.↗

NASA NTRS1978

Time-delay-and-integration charge-coupled devices using tin oxide gate technology

Doped tin oxide gates are used in a time-delay-and-integration (TDI) CCD scheme in an effort to develop a stable transparent gate technology. Design characteristics of the system are discussed, including 2 sections of 10 by 9 integration stages, four-phase buried channel construction, and 10 input parallel-in/serial-out output shift register at a video rate of 1.25 MHz. A quantum efficiency of 65% with smooth spectral response is attained by front surface imaging. The suitability of the system for the Landsat program is discussed in terms of TDI-CCD operating parameters.

Thompson, L. L.↗

NASA NTRS1978

Investigation of the dynamic range problem and providing software support for the AOL system

The present scheme for providing system timing for the airborne oceanographic lidar (AOL) system is not completely satisfactory. The possibility of using a digital approach to generate the forty pulses needed to energize the gates leading to the charge digitizers was investigated. The solution in terms of general analog and digital circuitry is straightforward. The crystal oscillator provides a stable frequency source which is used as a clock to the ring counter. The ring counter propagates a pulse from stage one to stage forty. Each of the outputs has an amplifier for isolation. This design is easy to implement in the frequency range up to 50 MHZ. Because a gate pulse width of from about 2 to 6 ns is needed for the AOL system, this dictates an input clock frequency to the shift register of from 100 MHA to 500 MHA. Problems associated with generating pulses in this range of operation are examined and an alternate solution is discussed.

Source record↗

NASA NTRS1979

The effect of interference on delta modulation encoded video signals

The results of a study on the use of the delta modulator as a digital encoder of television signals are presented. The computer simulation was studied of different delta modulators in order to find a satisfactory delta modulator. After finding a suitable delta modulator algorithm via computer simulation, the results are analyzed and then implemented in hardware to study the ability to encode real time motion pictures from an NTSC format television camera. The effects were investigated of channel errors on the delta modulated video signal and several error correction algorithms were tested via computer simulation. A very high speed delta modulator was built (out of ECL logic), incorporating the most promising of the correction schemes, so that it could be tested on real time motion pictures. The final area of investigation concerned itself with finding delta modulators which could achieve significant bandwidth reduction without regard to complexity or speed. The first such scheme to be investigated was a real time frame to frame encoding scheme which required the assembly of fourteen, 131,000 bit long shift registers as well as a high speed delta modulator. The other schemes involved two dimensional delta modulator algorithms.

Schilling, D. L.↗

NASA NTRS1979

Quick-look decoding schemes for DSN convolutional codes

Decoding schemes are proposed for the tracking systems of the galileo project. Quick look decoding schemes requiring only shift registers are given for the DSN (7, 1/2) and (7, 1/3) convolutional codes. These schemes are used when the communication channel is error free. The schemes decode the data, symbol errors, and the lack of node syncronization.

Greenhall, C. A.↗

NASA NTRS1977

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗

NASA NTRS1978

Implementation of real-time digital signal processing systems

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Narasimha, M.↗

NASA NTRS1979

A /31,15/ Reed-Solomon Code for large memory systems

This paper describes the encoding and the decoding of a (31,15) Reed-Solomon Code for multiple-burst error correction for large memory systems. The decoding procedure consists of four steps: (1) syndrome calculation, (2) error-location polynomial calculation, (3) error-location numbers calculation, and (4) error values calculation. The principal features of the design are the use of a hardware shift register for both high-speed encoding and syndrome calculation, and the use of a commercially available (31,15) decoder for decoding Steps 2, 3 and 4.

Lim, R. S.↗

NASA NTRS1980

Independent synchronizer for digital decoders

Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.

Stiffler, J. J.↗

NASA NTRS1979

Cosmic ray-induced soft errors in static MOS memory cells

Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.

Sivo, L. L.↗