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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

A software simulation study of a (255,223) Reed-Solomon encoder-decoder

A set of software programs which simulates a (255,223) Reed-Solomon encoder/decoder pair is described. The transform decoder algorithm uses a modified Euclid algorithm, and closely follows the pipeline architecture proposed for the hardware decoder. Uncorrectable error patterns are detected by a simple test, and the inverse transform is computed by a finite field FFT. Numerical examples of the decoder operation are given for some test codewords, with and without errors. The use of the software package is briefly described.

Pollara, F.↗
NASA NTRS1987

Attaching Copper Wires to Magnetic-Reed-Switch Leads

Bonding method reliably joins copper wires to short iron-alloy leads from glass-encased dry magnetic-reed switch without disturbing integrity of glass-to-metal seal. Joint resistant to high temperatures and has low electrical resistance.

Kamila, Rudolf↗
NASA NTRS1986

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Hsu, I. S.↗
NASA NTRS1987

Reed-Solomon decoder

A Reed-Solomon decoder with dedicated hardware for five sequential algorithms was designed with overall pipelining by memory swapping between input, processing and output memories, and internal pipelining through the five algorithms. The code definition used in decoding is specified by a keyword received with each block of data so that a number of different code formats may be decoded by the same hardware.

Lahmeyer, Charles R.↗
NASA NTRS1987

The binary weight distribution of the extended (2 sup m, 2 sup m-4) code of Reed-Solomon code over GF(2 sup m) with generator polynomial (x-alpha sup 2) (x-alpha sup 3)

Consider an (n,k) linear code with symbols from GF(2 sup m). If each code symbol is represented by a binary m-tuple using a certain basis for GF(2 sup m), a binary (nm,km) linear code called a binary image of the original code is obtained. A lower bound is presented on the minimum weight enumerator for a binary image of the extended (2 sup m, 2 sup m -4) code of Reed-Solomon code over GF(2 sup m) with generator polynomical (x - alpha)(x- alpha squared)(x - alpha cubed) and its dual code, where alpha is a primitive element in GF(2 sup m).

Lin, Shu↗
NASA NTRS1986

VLSI Reed Solomon decoder design

A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80 Mbits/second. A total of seven chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.

Maki, Gary K.↗
NASA NTRS1988

Single-Chip VLSI Reed-Solomon Decoder

Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.

Shao, Howard M.↗
NASA NTRS1987

Decoding of DBEC-TBED Reed-Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256 K bit DRAM's are organized in 32 K x 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. The paper presents a special decoding technique for double-byte-error-correcting, triple-byte-error-detecting RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Deng, Robert H.↗
NASA NTRS1989

More On The Decoder-Error Probability Of Reed-Solomon Codes

Paper extends theory of decoder-error probability for linear maximum-distance separable (MDS) codes. General class of error-correcting codes includes Reed-Solomon codes, important in communications with distant spacecraft, military communications, and compact-disk recording industry. Advancing beyond previous theoretical developments that placed upper bounds on decoder-error probabilities, author derives an exact formula for probability PE(u) that decoder will make error when u code symbols in error.

Cheung, Kar-Ming↗
NASA NTRS1989

Performance of concatenated codes using 8-bit and 10-bit Reed-Solomon codes

The performance improvement of concatenated coding systems using 10-bit instead of 8-bit Reed-Solomon codes is measured by simulation. Three inner convolutional codes are considered: (7,1/2), (15,1/4), and (15,1/6). It is shown that approximately 0.2 dB can be gained at a bit error rate of 10(-6). The loss due to nonideal interleaving is also evaluated. Performance comparisons at very low bit error rates may be relevant for systems using data compression.

Pollara, F.↗
NASA NTRS1991

Reed Valve Regulates Welding Back-Purge Pressure

Simple modification yields welds of better quality. Reed valve halves fluctuations in pressure in back-purge chamber attached to workpiece undergoing keyhole plasma arc welding. Identical to one used in fuel system of two-cycle gasoline engine. Backbead smoother, and weld penetrates more uniformly.

Coby, J. Ben, Jr.↗
NASA NTRS1991

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

Hsu, In-Shek↗
NASA NTRS1990

Performance of concatenated Reed-Solomon trellis-coded modulation over Rician fading channels

A concatenated coding scheme for providing very reliable data over mobile-satellite channels at power levels similar to those used for vocoded speech is described. The outer code is a shorter Reed-Solomon code which provides error detection as well as error correction capabilities. The inner code is a 1-D 8-state trellis code applied independently to both the inphase and quadrature channels. To achieve the full error correction potential of this inner code, the code symbols are multiplexed with a pilot sequence which is used to provide dynamic channel estimation and coherent detection. The implementation structure of this scheme is discussed and its performance is estimated.

Moher, Michael L.↗
NASA NTRS1992

VLSI architecture for a Reed-Solomon decoder

A basic single-chip building block for a Reed-Solomon (RS) decoder system is partitioned into a plurality of sections, the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10 and 8 bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10 and 8 bit operation.

Hsu, In-Shek↗
NASA NTRS1991

SEU hardened memory cells for a CCSDS Reed-Solomon encoder

A design technique to harden CMOS memory circuits against single event upset (SEU) in the space environment is reported. The design technique provides a recovery mechanism which is independent of the shape of the upsetting event. A RAM cell and flip-flop design are presented to demonstrate the method. The flip-flop was used in the control circuitry for a Reed-Solomon encoder designed for the Space Station and Explorer platforms.

Whitaker, Sterling↗
NASA NTRS1992

Binary weight distributions of some Reed-Solomon codes

The binary weight distributions of the (7,5) and (15,9) Reed-Solomon (RS) codes and their duals are computed using the MacWilliams identities. Several mappings of symbols to bits are considered and those offering the largest binary minimum distance are found. These results are then used to compute bounds on the soft-decoding performance of these codes in the presence of additive Gaussian noise. These bounds are useful for finding large binary block codes with good performance and for verifying the performance obtained by specific soft-coding algorithms presently under development.

Pollara, F.↗
NASA NTRS1994

Mapping Between Distinct Reed-Solomon Codes

One-to-one mapping between two Reed-Solomon (RS) codes devised to enable decoder designed for one of codes to operate on other one also. Codes in question must have same N and K parameters (defined below) but otherwise be two distinct RS codes. Mapping intended to enable same ground-based decoder to decode telemetry signals from two spacecraft in two different RS codes of (N,K) = (255,223). Also useful in purely terrestrial data communications and in optical and magnetic recording and playback of digitized audio and video signals. Implemented in interface circuitry and/or software to enable communication between coding systems of different manufacturers using different RS codes within same (N,K) family.

Perlman, Marvin↗