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Study consisted of an analytical approach, in which a mathematical model of existing printed circuit board component mounting techniques was analyzed, and an empirical investigation was performed to determine the extent of damage caused by temperature cycling of the printed circuit boards.
An improved design concept for a printed-circuit patch antenna and the transmission line that feeds the patch calls for (1) a microstrip transmission line on the front (radiative) side of a printed-circuit board based on a thin, high-permittivity dielectric substrate; (2) using the conductor covering the back side of the circuit board as a common ground plane for both the microstrip line and the antenna patch; (3) supporting the antenna patch in front of the circuit board on a much thicker, lower-permittivity dielectric spacer layer; and (4) connecting the microstrip transmission line to the patch by use of a thin wire or narrow ribbon that extends through the thickness of the spacer and is oriented perpendicularly to the circuit-board plane. The thickness of the substrate is typically chosen so that a microstrip transmission line of practical width has an impedance between 50 and 100 ohms. The advantages of this design concept are best understood in the context of the disadvantages of prior design concepts, as explained
Trace Laboratories is an independent testing laboratory specializing in testing printed circuit boards, automotive products and military hardware. Technical information from NASA Tech Briefs and two subsequent JPL Technical Support packages have assisted Trace in testing surface insulation resistance on printed circuit board materials. Testing time was reduced and customer service was improved because of Jet Propulsion Laboratory technical support packages.
This disk contains both a FORTRAN computer program and the corresponding user's guide that facilitates both its incorporation into your system and its utility. The computer program represents an efficient algorithm that routes signal traces on layers of a printed circuit with both through-pins and surface mounts. The computer program included is an implementation of the ideas presented in the theoretical paper titled "A Formal Algorithm for Routing Signal Traces on a Printed Circuit Board", NASA TP-3639 published in 1996. The computer program in the "connects" file can be read with a FORTRAN compiler and readily integrated into software unique to each particular environment where it might be used.
Planar capacitor made on epoxy/fiberglass printed-circuit board. Planar design and flat copper plates ensure low inductance and low series resistance. Planar construction minimized effects of thermal contraction, and epoxy/fiberglass substrate ensured high breakdown voltage. Design is simple, and this type of capacitor easy for any printed-circuit-board facility to fabricate. Design suitable for any small-capacitance, high-voltage capacitor, whether operating at low or high temperature.
Helium gas loops have been designed and built to gain a better understanding of the gas thermohydraulic phenomena that take place in a helium system. Some of these loops are used for validation and testing of components for high temperature gas-cooled reactors (HTGRs). However, most of them operate at lower pressure and temperature than an HTGR. While these loops can provide valuable information about gas-cooled reactor components, the operating envelope of the experiment is constrained by the maximum operating conditions of the helium loop. In response to the lack of an experimental facility that can provide the infrastructure needed to validate and test components at nominal pressures and temperatures of HTGRS, the HElium Component Testing Out-of-pile Research (HECTOR) facility was designed at Idaho National Laboratory with the assistance of University of Idaho and Walsh Engineering. With the capability to test at temperatures up to 800°C and pressures of 8MPa, HECTOR serves as a critical tool for the advancement of HTGR technology. The facility's primary role is to provide a controlled, high-fidelity environment for the assessment of component resilience and efficiency under nominal HTGR conditions. In the quest to enhance the efficiency and performance of HECTOR, a comparative analysis of three distinct types of heat exchangers—shell and tube, offset strip fin, and printed-circuit—was conducted, focusing primarily on two critical metrics: the required surface area and pressure drop characteristics. The shell and tube heat exchanger, renowned for its robust design and widespread industrial application, was evaluated against the offset strip fin and the cuttingedge printed-circuit heat exchangers, both of which are lauded for their compactness and thermal effectiveness. This comparative study aims to provide detailed insights into the thermal management capabilities of each heat exchanger type under the conditions inherent to HECTOR, thereby facilitating an informed selection for systems demanding high operational integrity and efficiency.
The network, which is connected to a layer of 134 feed elements that transmit and receive microwaves, consists of a pair of circuit boards parallel to the feed element layer. One of the two boards has 87 dividers that each divide a signal to be transmitted into seven portions, and the other board has 134 combiners that each collect seven transmit signal portions and deliver the sum to one of the feed elements. A similar arrangement is used to handle received signals. The large number of interconnections are made by printed circuit conductors radiating from each of the numerous dividers and combiners, and by providing interconnection pins that interconnect the ends of pairs of conductors lying on the two boards. The printed circuit conductors extend in undulating paths that provide maximum separation of conductors to minimize crosstalk.
Emerging satellite designs require increasing amounts of electrical power to operate spacecraft instruments and to provide environments suitable for human habitation. In the past, electrical power was generated by covering rigid honeycomb panels with solar cells. This technology results in unacceptable weight and volume penalties when large amounts of power are required. To fill the need for large-area, lightweight solar arrays, a fabrication technique in which solar cells are attached to a copper printed circuit laminated to a plastic sheet was developed. The result is a flexible solar array with one-tenth the stowed volume and one-third the weight of comparably sized rigid arrays. An automated welding process developed to attack the cells to the printed circuit guarantees repeatable welds that are more tolerant of severe environments than conventional soldered connections. To demonstrate the flight readiness of this technology, the Solar Array Flight Experiment (SAFE) was developed and flown on the space shuttle Discovery in September 1984. The tests showed the modes and frequencies of the array to be very close to preflight predictions. Structural damping, however, was higher than anticipated. Electrical performance of the active solar panel was also tested. The flight performance and postflight data evaluation are described.
In 2014, in response to a large volume of feedback from industry, the science community, and internal to Goddard Space Flight Center (GSFC), GSFC’s Safety and Mission Assurance (SMA) Directorate began a transition to a risk-based implementation of SMA, departing from its longstanding practice of being primarily driven by a mostly static set of Mission Assurance Requirements. The transition started out with a pilot project involving risk-based acceptance of bare-printed circuit boards that was enormously successful, continued through a complete organizational transformation in 2015, and culminated with the baselining of formal Risk-Based SMA policy in 2016. In this presentation we will describe the risk-based SMA concept, segue into how it shapes a modernization of risk classification that GSFC has rolled out, and provide results from the original pilot project for risk-based SMA, involving the printed circuit board assurance process.
Current capabilities of CubeSats must be improved in order to perform more ambitious missions. Electric propulsion systems will play a key role due to their large specific impulse. Compared to other propulsion alternatives, their simplicity allows an easier miniaturization and manufacturing of autonomous modules into the nano and pico-satellite platform. Pulsed Plasma Thrusters (PPTs) appear as one of the most promising technologies for the near term. The utilization of solid and non-volatile propellants, their low power requirements and their proven reliability in the large scale make them great candidates for rapid implementation. The main challenges are the integration and miniaturization of all the electronic circuitry into a printed circuit board (PCB) that can satisfy the strict requirements that CubeSats present. NASA Ames and the George Washington University have demonstrated functionality and control of three discrete Micro-Cathode Arc Thrusters (CAT) using a bench top configuration that was compatible with the ARC PhoneSat Bus. This demonstration was successfully conducted in a vaccum chamber at the ARC Environmental Test Laboratory. A new effort will integrate a low power Plasma Processing Unit and two plasma thrusters onto a single printed circuit board that will utilize less than 13 U of Bus volume. The target design will be optimized for the accommodation into the PhoneSatEDISON Demonstration of SmallSatellite Networks (EDSN) bus as it uses the same software interface application, which was demonstrated in the previous task. This paper describes the design, integration and architecture of the proposed propulsion subsystem for a planned Technology Demonstration Mission. In addition, a general review of the Pulsed Plasma technology available for CubeSats is presented in order to assess the necessary challenges to overcome further development.
A worst case assessment was performed on the Command Data System (CDS) multilayer printed circuit board and an output power transformer module in the power subsystem. An estimate of the Jovian environment during the 35 hour orbit insertion was supplied by JPL and used as an input to calculate the electron transport into the Galileo components. A radiation shielding analysis computer code, CHARGE, calculated the electron transport deposition trapped in the anticipated sensitive areas of the multilayer board and transformer module. Based on these trapped charge calculations electric fields were calculated between the identified isolated areas and the spacecraft ground. The results of the assessment of electrostatic discharge (DSD) in the CDS multilayer printed circuit board indicate that the probability of ESD in the FR4 is low. The probability of ESD in the components attached to the multilayer board, however, is uncertain based on a lack of prior experimental data.
NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.
This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.
This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.
This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.
Ion mobility separations are usually performed in linear channels, which, when extended, can have a large footprint. In this work, we explored the performance of an ion mobility device with a curved architecture which can have a more compact form. The Co-centric Ion Mobility Spectrometer (CIMS) works by manipulating ions between two co-centric surfaces, each containing a serpentine track. The mobility separation inside CIMS is achieved using traveling waveforms (TWs). We initially evaluated the device using ion trajectory simulations using SIMION, which indicated that when ions traveled circularly inside CIMS, they resulted in similar resolving powers and transmitted m/z range as traveling in a straight path in structures for lossless ion manipulations (SLIM). We then performed experimental validation of CIMS in conjunction with a TOF MS. The CIMS was made of 2 flexible printed circuit board materials folded into concentric cylinders separated by a gap of 2.8 mm. The device was about 50 mm diameter × 152 mm long and provided 1.846 m of serpentine path length. Three sets of mixtures (Agilent tune mixture, tetraalkylammonium salts, and 8 peptide mixture) and four traveling waveform profiles (square, sine, triangle, and sawtooth) were used. The sawtooth TW profile produced a slightly higher resolving power for the Agilent tuning mixture and tetraalkylammonium ions. The average resolving power for Agilent tune mixture ions ranged from 37 (using sawtooth TW) to 27 (using square TW). For tetraalkylammonium ions, the average resolving powers ranged from 45 (sawtooth TW) to 31 (square TW). For the peptide mixture ions, the resolving power was similar among the four TW profiles and ranged from 51 to 56. The average percent error in TW CCS for the peptide mixture ions ranged was about 0.4%. In conclusion, the new device showed promising results for a device made of a flexible printed circuit board material, but improvements are needed to further increase the resolving power.
This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by MSFC Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data from two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMCIRA design has completed all engineering unit testing and the deliverable unit is currently under development.
This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by Marshall Space Flight Center (MSFC) Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data fiom two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMC-IRA design has completed all engineering and deliverable unit testing. P