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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

NREL 25-cm2 High-Pressure Low-Temperature Electrolysis Cell Hardware (Open Source)

This data resource describes an open-source cell hardware that enables low temperature electrolysis (LTE) testing at elevated pressures. Existing commercial options have several downsides when it comes to R&D testing. They are often not designed for repeated reassembly, may not be able to accommodate porous transport layers with different thicknesses, and do not give state-of-the-art performance. Therefore, this hardware was developed specifically with LTE R&D in mind and its design is being made available to the global LTE community. This work was planned and funded by the U.S. Department of Energy's H2NEW consortium (https://h2new.energy.gov/). The hardware design package (.zip file) details the drawings, auxiliary materials, and procedures required to fabricate, assemble, and operate the National Renewable Energy Laboratory's (NREL's) high-pressure low-temperature electrolysis cells. While the hardware itself—end plates, current collectors, flow fields, bolts and washers, tube fittings—is always the same, the assembly and operating procedures may change depending on the active materials being tested, especially for the membrane. Material-specific assembly and operating procedures will be posted to the H2NEW website as they are developed and validated. Disclaimer: The documents and drawings included in this download package describe a design for a low temperature electrolysis hardware that is intended to comply with leak testing according to ASME B31.1. Safe operation at ambient and elevated pressures is the sole responsibility of the end user, which should be evaluated on a case-by-case basis for each individual cell. Factors affecting the sealing capability may depend on, for example, machining quality, cell assembly components, operating conditions, and operating history. Operation at pressure should only be performed on qualified test stands by qualified operators. NREL/ALLIANCE FOR SUSTAINABLE ENERGY, LLC/DOE DISCLAIM ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, AND MAKES NO WARRANTY AS TO THE ACCURACY, COMPLETENESS, OR USEFULNESS OF ANY INFORMATION PROVIDED HEREIN. USE OF THIS PACKAGE IS AT THE USER’S OWN RISK.

08 HYDROGEN↗
DOE OSTI2022

Advanced Power-Hardware-in-the-Loop Evaluation of Inverter-Based Resources (IBRs)

Power-hardware-in-the-loop evaluation of IBRs has become more and more important as it provides reliable testing results to investigate the real responses of inverters with interconnected systems. A successful laboratory PHIL testing gives confidence of the hardware system to be deployed and de-risk technology integration prior to field deployment. So far, there are two important applications for PHIL evaluation: (1) test stability and functionality of large utility inverters into the system when it interconnects to the distribution systems/microgrids; and (2) test the collective grid service that inverters can provide to the grid. For the first application, the PHIL evaluation has high requirements for the stability and accuracy of the PHIL interface as the close-loop in digital real time simulator (DRTS) should replicate the actual current and voltage dynamics in the inverter. This is challenging because of the delays, sensing errors, nonlinearities of inverters, and hardware bandwidth limitations of the elements in the HIL loop. For the second application, multiple inverters will be tested resulting in multiple PCCs, which naturally causes competing dynamics and oscillations among hardware inverters if traditional PHIL interface is used. Therefore, new PHIL interface should be developed to compromise between stability and accuracy and represent the dispatched grid services for the hardware inverters. In this presentation, we will share our latest work in developing PHIL interface in these two applications to address the two key challenges.

DERMS↗
DOE OSTI2017

A historical survey of algorithms and hardware architectures for neural-inspired and neuromorphic computing applications

In this study, biological neural networks continue to inspire new developments in algorithms and microelectronic hardware to solve challenging data processing and classification problems. Here in this research, we survey the history of neural-inspired and neuromorphic computing in order to examine the complex and intertwined trajectories of the mathematical theory and hardware developed in this field. Early research focused on adapting existing hardware to emulate the pattern recognition capabilities of living organisms. Contributions from psychologists, mathematicians, engineers, neuroscientists, and other professions were crucial to maturing the field from narrowly-tailored demonstrations to more generalizable systems capable of addressing difficult problem classes such as object detection and speech recognition. Algorithms that leverage fundamental principles found in neuroscience such as hierarchical structure, temporal integration, and robustness to error have been developed, and some of these approaches are achieving world-leading performance on particular data classification tasks. Additionally, novel microelectronic hardware is being developed to perform logic and to serve as memory in neuromorphic computing systems with optimized system integration and improved energy efficiency. Key to such advancements was the incorporation of new discoveries in neuroscience research, the transition away from strict structural replication and towards the functional replication of neural systems, and the use of mathematical theory frameworks to guide algorithm and hardware developments.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Prometheus: Coherent Exploration of Hardware and Software Optimizations using Aspen

With the dramatic increase in scale expected for Exascale computing, there is a dire need for tuning of hardware configurations and software optimizations such that they are in unison. However, the expected increase in tunable hardware parameters makes searching through the design space for optimal hardware-and-software configurations much more challenging. Towards this end, we propose a composable hardware-software optimization framework called Prometheus. Prometheus uses a combination of analytical and machine-learning techniques to capture application characteristics and subsequently determine the hardware-software configuration for near-optimal performance. We evaluate Prometheus for its efficacy using four widely used proxy applications: LULESH, CoMD, CG and CoEVP. We demonstrate that Prometheus identifies near-optimal hardwaresoftware configurations and verify the results via brute-force search of the design space.

Umar, Mariam↗
DOE OSTI2022

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

Transformers are considered one of the most important deep learning models since 2018, in part because it establishes state-of-the-art (SOTA) records and could potentially replace existing Deep Neural Networks (DNNs). Despite the remarkable triumphs, the prolonged turnaround time of Transformer models is a widely recognized roadblock. The variety of sequence lengths imposes additional computing overhead where inputs need to be zero-padded to the maximum sentence length in the batch to accommodate the parallel computing platforms. This paper targets the field-programmable gate array (FPGA) and proposes a coherent sequence length adaptive algorithm–hardware co-design for Transformer acceleration. Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm. The proposed sparse attention operator brings the complexity of attention-based models down to linear complexity and alleviates the off-chip memory traffic. The proposed length-aware resource hardware scheduling algorithm dynamically allocates the hardware resources to fill up the pipeline slots and eliminates bubbles for NLP tasks. Experiments show that our design has very small accuracy loss and has 80.2 × and 2.6 × speedup compared to CPU and GPU implementation, and 4 × higher energy efficiency than state-of-the-art GPU accelerator optimized via CUBLAS GEMM.

Peng, Hongwu↗
DOE OSTI2024

Modernizing Fermilab's Accelerator Control Hardware

Modernizing the Fermilab accelerator control system is essential to future operations of the laboratory's accelerator complex. The existing control system has evolved over four decades and uses hardware that is no longer available.The Accelerator Controls Operations Research Network (ACORN) Project will modernize the control system and replace end-of-life power supplies to enable future accelerator complex operations with megawatt particle beams. The ACORN project is planning to replace Fermilab s obsolete CAMAC crate-and-card controls hardware with modern MicroTCA hardware. There are over 2,000 CAMAC cards and over 250 CAMAC crates serving various functions in Fermilab s control system. We will review the existing CAMAC hardware and provide updates on the status of the ACORN project, which includes the conceptual design of the MicroTCA replacement hardware and software tools for supporting the installation of hundreds of MicroTCA crates.

43 PARTICLE ACCELERATORS↗
NASA NTRS1974

An evaluation of Skylab habitability hardware

For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

Stokes, J.↗
NASA NTRS1975

Development and characteristics of the hardware for Skylab experiment S015

Details are given regarding the hardware for the Skylab S015 experiment, which was designed to detect the effects of zero gravity on cell growth rates. Experience gained in hardware-related considerations is presented for use of researchers concerned with future research of this type and further study of the S015 results. Brief descriptions are given of the experiment hardware, the hardware configuration for the critical design review, the major configuration changes, the final configuration, and the postflight review and analysis. An appendix describes pertinent documentation, film, and hardware that are available to qualified researchers; sources for additional or special information are given.

Thirolf, R. G.↗
NASA NTRS1992

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Moore, J. Strother↗
NASA NTRS1990

Space Station Freedom biomedical monitoring and countermeasures: Biomedical facility hardware catalog

This hardware catalog covers that hardware proposed under the Biomedical Monitoring and Countermeasures Development Program supported by the Johnson Space Center. The hardware items are listed separately by item, and are in alphabetical order. Each hardware item specification consists of four pages. The first page describes background information with an illustration, definition and a history/design status. The second page identifies the general specifications, performance, rack interface requirements, problems, issues, concerns, physical description, and functional description. The level of hardware design reliability is also identified under the maintainability and reliability category. The third page specifies the mechanical design guidelines and assumptions. Described are the material types and weights, modules, and construction methods. Also described is an estimation of percentage of construction which utilizes a particular method, and the percentage of required new mechanical design is documented. The fourth page analyzes the electronics, the scope of design effort, and the software requirements. Electronics are described by percentages of component types and new design. The design effort, as well as, the software requirements are identified and categorized.

Source record↗
NASA NTRS1993

Postflight hardware evaluation 360T025 (RSRM-25, STS-46)

The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the 360T025 (STS-46) Redesign Solid Rocket Motor (RSRM) flight set is presented. All observed hardware conditions were documented on PFOR's and are included in Appendices A through C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. Along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-60687), a summary of the 360T025 hardware evaluation is provided. The as-flown hardware configuration is documented in TWR-60470. Disassembly evaluation photograph numbers are logged in TWA-1986. The 360T025 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on 16 Mar. 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

Morgan, Ferral↗
NASA NTRS1993

Postflight hardware evaluation 360T026 (RSRM-26, STS-47)

The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the 360T026 (STS-47) Redesigned Solid Rocket Motor (RSRM) flight set is provided. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64203), represents a summary of the 360T026 hardware evaluation. The as-flown hardware configuration is documented in TWR-60472. Disassembly evaluation photograph numbers are logged in TWA-1987. The 360T026 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on 12 April 1993. Detailed evaluations were performed in accordance with the Clearfield Postflight Engineering Evaluation Plan (PEEP), TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

Nielson, Greg↗
NASA NTRS1993

Satellite Communication Hardware Emulation System (SCHES)

Satellite Communication Hardware Emulator System (SCHES) is a powerful simulator that emulates the hardware used in TDRSS links. SCHES is a true bit-by-bit simulator that models communications hardware accurately enough to be used as a verification mechanism for actual hardware tests on user spacecraft. As a credit to its modular design, SCHES is easily configurable to model any user satellite communication link, though some development may be required to tailor existing software to user specific hardware.

Kaplan, Ted↗
NASA NTRS1993

Final postflight hardware evaluation report RSRM-28 (STS-53)

The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-28 (STS-53) RSRM flight set is presented. All observed hardware conditions were documented on PFOR's and are included in Appendices A through C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64215), represents a summary of the RSRM-28 hardware evaluation. The as-flown hardware configuration is documented in TWR-63638. Disassembly evaluation photograph numbers are logged in TWA-1989. The RSRM-28 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on July 15, 1993. Additional time was required to perform the evaluation of the stiffener rings per special issue 4.1.5.2 because of the washout schedule. The release of this report was after completion of all special issues per program management direction. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable team and tracked through the PFAR system.

Starrett, William David, Jr.↗
NASA NTRS1992

VME rollback hardware for time warp multiprocessor systems

The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

Robb, Michael J.↗
NASA NTRS1993

Analysis of a hardware and software fault tolerant processor for critical applications

Computer systems for critical applications must be designed to tolerate software faults as well as hardware faults. A unified approach to tolerating hardware and software faults is characterized by classifying faults in terms of duration (transient or permanent) rather than source (hardware or software). Errors arising from transient faults can be handled through masking or voting, but errors arising from permanent faults require system reconfiguration to bypass the failed component. Most errors which are caused by software faults can be considered transient, in that they are input-dependent. Software faults are triggered by a particular set of inputs. Quantitative dependability analysis of systems which exhibit a unified approach to fault tolerance can be performed by a hierarchical combination of fault tree and Markov models. A methodology for analyzing hardware and software fault tolerant systems is applied to the analysis of a hypothetical system, loosely based on the Fault Tolerant Parallel Processor. The models consider both transient and permanent faults, hardware and software faults, independent and related software faults, automatic recovery, and reconfiguration.

Dugan, Joanne B.↗
NASA NTRS1995

Hardware cleanliness methodology and certification

Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

Harvey, Gale A.↗
NASA NTRS1998

Innovative Contamination Certification of Multi-Mission Flight Hardware

Maintaining contamination certification of multi-mission flight hardware is an innovative approach to controlling mission costs. Methods for assessing ground induced degradation between missions have been employed by the Hubble Space Telescope (HST) Project for the multi-mission (servicing) hardware. By maintaining the cleanliness of the hardware between missions, and by controlling the materials added to the hardware during modification and refurbishment both project funding for contamination recertification and schedule have been significantly reduced. These methods will be discussed and HST hardware data will be presented.

Hansen, Patricia A.↗