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Circuit proposed to recover energy usually lost in charging and discharging internal gate capacitance of field-effect transistor during high-frequency switching. Scheme includes pulse-forming circuit generating rectangular waveform with zero-level notches near beginning and end of "on" period. Inductor resonates internal gate capacitance so energy recovered during notches.
The fabrication and performance of an Al(0.3)Ga(0.7)As/GaAs modulation-doped resistive-gate CCD are reported. The two-dimensional electron gas (2DEG) CCD, implemented as a 32-stage four-phase delay line, was tested at both low (1-13 MHz) and high (0.6-1.0 GHz) frequency. It exhibits a room-temperature charge-transfer efficiency (CTE) of better than 0.999 at clock frequencies from 10 MHz up to 1 GHz without a fat-zero signal and is limited by dark current below 10 MHz. The high-frequency test showed no CTE degradation up to 1-GHz operation. The CTE degraded at frequencies lower than approximately 5 MHz due to dark current. The charge-handling capability and minimum clock swing of the resistive-gate 2DEG CCD are calculated.
Ammonium-sulfide (NH4)2S treated gates have been employed in the fabrication of GaAs MESFETs that exhibit a remarkable reduction in subthreshold leakage current. A greater than 100-fold reduction in drain current minimum is observed due to a decrease in Schottky gate leakage. The electrical characteristics have remained stable for over a year during undesiccated storage at room temperature, despite the absence of passivation layers.
Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.
Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.
Concerning our knowledge of convective clouds and their important processes, GATE marks a watershed between "seeing through a glass darkly" and "then face to face" in some of the most vital aspects of convective systems. Two main areas will be discussed here, namely the interactions of observations and modeling in documentation of slow and fast-moving squall lines, for which the publications began in the 70's, and the use of the GATE ships' radar data set as the basis for demonstrating that tropical rainfall could be measured from space, resulting in the Tropical Rainfall Measuring Mission (TRMM). The TRMM satellite was launched in 1997, with the enabling analyses reaching publication in the 1980's.
This paper reports on an initial assessment of using a Field-Programmable Gate Array (FPGA) computational device as a new tool for solving structural mechanics problems. A FPGA is an assemblage of binary gates arranged in logical blocks that are interconnected via software in a manner dependent on the algorithm being implemented and can be reprogrammed thousands of times per second. In effect, this creates a computer specialized for the problem that automatically exploits all the potential for parallel computing intrinsic in an algorithm. This inherent parallelism is the most important feature of the FPGA computational environment. It is therefore important that if a problem offers a choice of different solution algorithms, an algorithm of a higher degree of inherent parallelism should be selected. It is found that in structural analysis, an 'analog computer' style of programming, which solves problems by direct simulation of the terms in the governing differential equations, yields a more favorable solution algorithm than current solution methods. This style of programming is facilitated by a 'drag-and-drop' graphic programming language that is supplied with the particular type of FPGA computer reported in this paper. Simple examples in structural dynamics and statics illustrate the solution approach used. The FPGA system also allows linear scalability in computing capability. As the problem grows, the number of FPGA chips can be increased with no loss of computing efficiency due to data flow or algorithmic latency that occurs when a single problem is distributed among many conventional processors that operate in parallel. This initial assessment finds the FPGA hardware and software to be in their infancy in regard to the user conveniences; however, they have enormous potential for shrinking the elapsed time of structural analysis solutions if programmed with algorithms that exhibit inherent parallelism and linear scalability. This potential warrants further development of FPGA-tailored algorithms for structural analysis.
The past funding period was productive for the group. The progress in the mechanosensitive channel field was critically affected in the end of 1998 by the solution of the crystal structure of the mycobacterial homolog of MscL by our colleagues from Caltech. Having the structure of TbMscL in the closed state, we developed a detailed homology model of EcoMscL, and related the structural model with the wealth of functional phenomenology available for the E. coli version of the channel (EcoMscL). The biophysical properties of the open MscL helped to model the open conformation and infer the pathway for the entire gating transition. The following experiments provided strong support to the atomic model of the gating process, and allowed to make further predictions. The work has advanced our understanding of tension-driven conformational transitions in membrane-embedded mechanosensory proteins, determine major energetic contributions and set the stage for further exploration of the whole family of mechanosensitive channels. The results have been published in seven experimental and theoretical papers, with three other papers currently in press or in preparation.
Real clouds and cloud systems are inherently three-dimensional (3D). Because of the limitations in computer resources, however, most cloud-resolving models (CRMs) today are still two-dimensional (2D). A few 3D CRMs have been used to study the response of clouds to large-scale forcing. In these 3D simulations, the model domain was small, and the integration time was 6 hours. Only recently have 3D experiments been performed for multi-day periods for tropical cloud systems with large horizontal domains at the National Center for Atmospheric Research (NCAR), NOAA GFDL, the U.K. Met. Office, Colorado State University and NASA Goddard Space Flight Center. An improved 3D Goddard Cumulus Ensemble (GCE) model was recently used to simulate periods during TOGA COARE (December 19-27, 1992), GATE (september 1-7, 1974), SCSMEX (May 18-26, June 2-11, 1998) and KWAJEX (August 7-13, August 18-21, and August 29-September 12, 1999) using a 512 by 512 km domain and 41 vertical layers. The major objectives of this paper are: (1) to identify the differences and similarities in the simulated precipitation processes and their associated surface and water energy budgets in TOGA COARE, GATE, KWAJEX, and SCSMEX, and (2) to asses the impact of microphysics, radiation budget and surface fluxes on the organization of convection in tropics.
We describe a method for achieving arbitrary 1-qubit gates and controlled-NOT gates within the context of the Single Cooper Pair Box (SCB) approach to quantum computing.
A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.
A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.
A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.
A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.
A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).
We describe an architecture for spontaneous Raman scattering utilizing a frame-transfer CCD sensor operating in a subframe burst-gating mode to realize time-resolved combustion diagnostics. The technique permits all-electronic optical gating with microsecond shutter speeds 5 J.Ls) without compromising optical throughput or image fidelity. When used in conjunction with a pair of orthogonally polarized excitation lasers, the technique measures single-shot vibrational Raman scattering that is minimally contaminated by problematic optical background noise.
The NASA Dust Management Project (DMP) was established to provide technologies (to TRL 6 development level) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, which will reduce life cycle cost and risk, and will increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product is either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.
The NASA Dust Management Project (DMP) was established to provide technologies (to Technology Readiness Level (TRL) 6) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, to reduce life cycle cost and risk, and to increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product was either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.