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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗
DOE OSTI2023

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.

do Amaral Custodio, Paulo Vitor↗
DOE OSTI2024

Towards Automated Generation of Chiplet-Based Systems

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application- Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a high-level frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This talk will discuss ongoing work on the SODA synthesizer to enable no-human-in-the-loop generation and design space exploration of the chiplets for highly specialized artificial intelligence accelerators. Connecting these highly specialized chiplets to general-purpose cores or programmable accelerators will allow to quickly deploy autonomous systems for scientific discovery.

Limaye, Ankur M.↗
DOE OSTI2024

A Graph Neural Network Surrogate Model for hls4ml

Recent advancements in use of machine learning (ML) techniques on field-programmable gate arrays (FPGAs) have allowed for the implementation of embedded neural networks with extremely low latency. This is invaluable for particle detectors at the Large Hadron Collider, where latency and used area are strictly bounded. The hls4ml framework is a procedure that converts trained ML model software to a synthesis result to can be used on an FPGA. However, running the pipeline is a time-consuming procedure, and there is a strong risk of failure. In particular, it may not be possible to successfully convert a model into a synthesis result, or the resource consumption of the model may exceed the resources of the target FPGA. To aid with this development, we introduce wa-hls4ml, a surrogate model using a graph neural network to emulate the structure of the source models. The goal is to estimate the chance of success and resource consumption of a given model when passed through the hls4ml pipeline, without needing to run the pipeline.

Plotnikov, Dennis↗
DOE OSTI2024

Calibration of the analog beam-signal hardware for the credited engineered beam power limit system at the Proton Power Upgrade Project at the Spallation Neutron Source

A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).

Bobrek, Miljko↗
DOE OSTI2025

SQuaD: Smart Quantum Detection for Photon Recognition and Dark Count Elimination

Quantum detectors of single photons are an essential component for quantum information processing across computing, communication and networking. Today's quantum detection system, which consists of single photon detectors, timing electronics, control and data processing software, is primarily used for counting the number of single photon detection events. However, it is largely incapable of extracting other rich physical characteristics of the detected photons, such as their wavelengths, polarization states, photon numbers, or temporal waveforms. This work, for the first time, demonstrates a smart quantum detection system, SQuaD, which integrates a field programmable gate array (FPGA) with a neural network model, and is designed to recognize the features of photons and to eliminate detector dark-count. The SQuaD is a fully integrated quantum system with high timing-resolution data acquisition, onboard multi-scale data analysis, intelligent feature recognition and extraction, and feedback-driven system control. Our \name experimentally demonstrates 1) reliable photon counting on par with the state-of-the art commercial systems; 2) high-throughput data processing for each individual detection events; 3) efficient dark count recognition and elimination; 4) up to 100% accurate feature recognition of photon wavelength and polarization. Additionally, we deploy the SQuaD to an atomic (erbium ion) photon emitter source to realize noise-free control and readout of a spin qubit in the telecom band, enabling critical advances in quantum networks and distributed quantum information processing.

Linne, Karl C. [U. Chicago (main)] (ORCID:00090009↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Schulte, Jan-Frederik [Purdue U.] (ORCID:000000034↗
DOE OSTI2025

Advancing \textit{otsdaq}: Enhancements for Usability, Accuracy, and Robustness

High-energy physics (HEP) experiments require data acquisition (DAQ) systems that can orchestrate complex detector operations, high data throughput, and responsive, real-time feedback to operators. Traditional DAQ stacks, which are often bespoke, command-line driven and highly specific, impose large learning curves on users. The Off-The-Shelf Data Acquisition (\textit{otsdaq}) framework was created to address these issues by offering a highly customizable and scalable browser-based ’desktop’ environment, in which experiment-specific control and monitoring applications can be easily deployed and integrated. Although the initial development of the \textit{otsdaq} software was aimed at the Fermilab Test Beam Facility, \textit{otsdaq} is now being leveraged for broader deployment, including the upcoming Mu2e experiment, where real-time monitoring of field-programmable gate array (FPGA)-based Data Transfer Controllers (DTCs), Clock and Fanout (CFO) boards, and several other subsystems are critical. We contribute a set of targeted improvements to \textit{otsdaq}: bitmap visualization functionality for configured data, improved and corrected delta-based DTC throughput metrics, version control (VC)-backed source navigation for console messages, custom navigation hooks to eliminate disruptive user interface glitches, and copy-to-clipboard support for macro execution history. These changes improve usability, reduce debugging time, and increase accuracy in performance data as Mu2e moves toward commissioning.

Mohammed, A. [Unlisted, US]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2021

Cooling and Timing Tests of the ATLAS Fast TracKer VME Boards

The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

Laser-induced fluorescence measurements of ion fluctuations in electron and ion presheaths

Electrostatic flow-driven instabilities have been predicted in the presheath region of low-temperature plasmas for both ion and electron rich sheaths. The ion-acoustic fluctuations that arise from these instabilities can influence transport through an enhanced collision rate. In this work, ion fluctuation spectra were measured using laser-induced fluorescence (LIF) in the presheath region for both sheath polarities. Furthermore, the non-invasive nature of LIF compared to that of probes is particularly valuable for these measurements because the sheath and presheath around a probe may generate their own flow-driven instabilities, which obscure the measurement. Measurements were made using a recently implemented field programmable gate array-based system able to measure ion fluctuation spectra up to 1 MHz using a two-point correlation function technique. Narrow bandwidth ion fluctuations were observed near 0:46 f pi (460 kHz) for both sheath polarities, where f pi is the ion plasma frequency. The observed fluctuations were significantly stronger in the electron sheath case and were observed over a larger volume of plasma. Fluctuations were measured in the ion sheath case at locations far enough from the sheath that linear theory predicts stability, suggesting that ion-acoustic instabilities generated in the relatively small unstable region near the boundary reflect from the sheath and perturb a much larger volume of the plasma. This is expected to affect probes with both ion and electron rich sheaths, meaning any dc biased probe may effectively act as an ion-acoustic wave antenna. These measurements are consistent with the recent theory and particle-in-cell results.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2023

Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis

Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Optical and x-ray characterization of the Daedalus ultrafast x-ray imager

The Daedalus ultrafast x-ray imager is the latest generation in Sandia’s hybrid CMOS detector family. With three frames along an identical line of sight, 1 ns minimum integration time, a higher full well than Icarus, and added features, Daedalus brings exciting new capabilities to diagnostic applications in inertial confinement fusion and high energy density science. In this work, we present measurements of time response, dynamic range, spatial uniformity, pixel cross-talk, and absolute x-ray sensitivity using pulsed optical and x-ray sources. Here, we report a measured 1.5 Me — full well, pixel sensitivity at 9.58 × 10 —7 V/e — , and an estimate of spatial uniformity at ~5% across the sensor array.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Overview and first measurements of the MAST Upgrade bolometer diagnostic

Here, a suite of multi-channel resistive bolometers has been implemented to measure the total radiation from Mega Amp Spherical Tokamak Upgrade plasmas, with cameras covering the core plasma and lower divertor chamber. Data are digitized and processed using novel field-programmable gate array-based electronics, offering improved compactness and new operational capabilities. A synthetic diagnostic has been developed to explore the quality of 2D reconstructions available from the system and to quantify the uncertainty on quantities such as the total radiated power. Measurements in the first campaign have demonstrated correct functioning of the diagnostic while also highlighting issues with electrical noise and some failure mechanisms of the detectors, as well as significant neutral beam fast-particle losses.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

A High-Speed, High-Resolution Transition Edge Sensor Spectrometer for Soft X-Rays at the Advanced Photon Source

This project explores the design and development of a transition edge sensor (TES) spectrometer for resonant soft X-ray scattering (RSXS) measurements developed in collaboration between Argonne National Laboratory (ANL) and the National Institute of Standards and Technology (NIST). Soft X-ray scattering is a powerful technique for studying the electronic and magnetic properties of materials on a microscopic level. However, the lack of high-performance soft X-ray spectrometers has limited the potential of this technique. TES spectrometers have the potential to overcome these limitations due to their high energy resolution, high efficiency, and broad energy range. This project aims to optimize the design of a TES spectrometer for RSXS measurements and more generally soft X-ray spectroscopy at the Advanced Photon Source (APS) 29-ID, leading to improved understanding of advanced materials. We will present a detailed description of the instrument design and implementation. The spectrometer consists of a large array of approximately 250 high-speed and high-resolution pixels. The pixels have saturation energies of approximately 1 keV, sub-ms pulse duration and energy resolution of approximately 1 eV. The array is read out using microwave multiplexing chips with MHz bandwidth per channel, enabling efficient data throughput. To facilitate measurement of samples in situ under ultra-high vacuum conditions at the beamline, the spectrometer is integrated with an approximately 1 m long snout.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

A PIPS + SrI 2 (Eu) detector for atmospheric radioxenon monitoring

The PIPS–SrI 2 (Eu) is a prototype atmospheric radioxenon detection system designed at Oregon State University in support of international efforts towards monitoring clandestine nuclear weapon testing activities. This detector aims to address some shortcomings found in currently deployed beta–gamma atmospheric radioxenon detection systems, such as lackluster energy resolution and memory effect, by employing modern detection materials and readout. The system uses a PIPSBox, a silicon-based gas cell, for electron detection, and a pair of ultrabright, D-shaped SrI 2 (Eu) scintillators coupled to silicon photomultipliers for photon detection. A custom eight-channel digital pulse processor equipped with a field programmable gate-array (FPGA) identifies electron–photon coincidences between the volumes in near real-time. Gas samples of the four radioxenon isotopes of interest were independently measured with the PIPS–SrI 2 (Eu) detection system to determine energy resolution and efficiency. Application of FPGA-based coincidence discrimination in near real-time reduced the ambient background count rate by 95.85 ± 0.04%. Using parameters from the Xenon International gas processing unit and assuming a blank sample and zero memory effect the minimum detectable concentrations (MDCs) for the isotopes were calculated to be 0.12 ± 0.03, 0.27 ± 0.05, 0.15 ± 0.02, and 1.00 ± 0.08 mBq/m 3 air for 131m Xe, 133 Xe, 133m Xe, and 135 Xe, respectively. These MDC estimates compare well with other radioxenon detection systems employed in the International Monitoring System (IMS) and indicate that the PIPS–SrI 2 (Eu) is in compliance with the Comprehensive Nuclear Test-Ban-Treaty Organization (CTBTO) sensitivity requirement of ≤ 1 mBq/m 3 for 133 Xe.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

High-power test of a C-band linear accelerating structure with an RFSoC-based LLRF system

Normal conducting linear particle accelerators consist of multiple rf stations with accelerating structure cavities. Low-level rf (LLRF) systems are employed to set the phase and amplitude of the field in the accelerating structure and to compensate for the pulse-to-pulse fluctuation of the rf field in the accelerating structures with a feedback loop. The LLRF systems are typically implemented with analog rf mixers, heterodyne-based architectures, and discrete data converters. There are multiple rf signals from each of the rf stations, so the number of rf channels required increases rapidly with multiple rf stations. With a large number of rf channels, the footprint, component cost, and system complexity of the LLRF hardware will increase significantly. To meet the design goals of being compact and affordable for future accelerators, we have designed the next-generation LLRF (NG-LLRF) with a higher integration level based on RFSoC technology. The NG-LLRF system samples rf signals directly and performs rf mixing digitally. Further, the NG-LLRF has been characterized in loopback mode to evaluate the performance of the system and has also been tested with a standing-wave accelerating structure, a prototype for the Cool Copper Collider (C 3 ) with a peak rf power level up to 16.45 MW. The loopback test demonstrated amplitude fluctuation below 0.15% and phase fluctuation below 0.15°, which are considerably better than the requirements of C 3 . The rf signals from the different stages of the accelerating structure at different power levels are measured by the NG-LLRF, which will be critical references for the control algorithm designs. The NG-LLRF also offers flexibility in waveform modulation, so we have used rf pulses with various modulation schemes, which could be useful for controlling some of the rf stations in accelerators. In this paper, the high-power test results at different stages of the test setup will be summarized, analyzed, and discussed.

47 OTHER INSTRUMENTATION↗