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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Low-temperature microwave characteristics of pseudomorphic In(x)Ga(1-x) As/In(0.52)Al(0.48)As modulation-doped field-effect transistors

Low-temperature microwave measurements of both lattice-matched and pseudomorphic In(x)Ga(1-x)As/In(0.48)As (x = 0.53, 0.60, and 0.70) channel MODFETs on InP substrates were carried out in a cryogenic measurement system. The measurements were done in the temperature range of 77 to 300 K and in the frequency range of 0.5 to 11.0 GHz at different bias conditions. The cutoff frequency (fT) for the In(x)Ga(1-x)As/In(0.52)Al(0.48)As MODFETs improved from 22 to 29 GHz, 29 to 38 GHz, and 39 to 51 GHz, for x = 0.53, 0.60, and 0.70, respectively, as the temperature was lowered from 300 to 77 K, which is approximately a 31 percent increase at each composition. No degradations were observed in device performance. These results indicate an excellent potential of the pseudomorphic devices at low temperatures.

Lai, R.↗
NASA NTRS1993

Ellipsometric characterization of In(0.52)Al(0.48)As and of modulation doped field effect transistor structures on InP substrates

The dielectric function of a thick layer of In(0.52)Al(0.48)As lattice matched to InP was measured by variable angle spectroscopic ellipsometry in the range 1.9-4.1 eV. The In(0.52)Al(0.48)As was protected from oxidation using a thin In(0.53)Ga(0.47)As cap that was mathematically removed for the dielectric function estimate. The In(0.52)Al(0.48)As dielectric function was then verified by ellipsometric measurements of other In(0.53)Ga(0.47)As/In(0.52)Al(0.48)As structures, including (MODFET), and is shown to provide accurate structure layer thicknesses.

Alterovitz, S. A.↗
NASA NTRS2002

Electrical Characterization of Polyaniline/polyethylene Oxide Nanofibers for Field Effect Transistors

Nanofibers comprised of polyaniline/polyethylene oxide (PANI/PEO) are being developed for novel logic devices. We report the electrical conductivity of PANI/PEO nanofibers with diameters in the 100 to 200 nm range. We measured conductivity values of approx. 0.3 to 1.0 S/cm, which is higher than the values reported for thicker nanofibers, but less than the bulk value of PANI. The electrical measurements were performed by depositing the fibers on pre-electroded, oxidized silicon (Si) substrates. The excellent adherence of the nanofibers to the SiO2 as well as the gold (Au) electrodes may be useful in the design of future devices.

Mueller, Carl H.↗
NASA NTRS2004

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

Miranda, Felix A.↗
NASA NTRS1999

Analysis of Carbon Nanotube Field-Effect-Transistors (FETs)

This five page presentation is grouped into 11 numbered viewgraphs, most of which contain one or more diagrams. Some of the diagrams are accompanied by captions, including: 2) Nanotube FET by Delft, IBM; 3) Nanotube FET/Standard MOSFET; 5) Saturation with carrier-carrier; 7) Electronic properties of carbon nanotube; 8) Theoretical nanotube FET characteristics; 11) Summary: Delft and IBM nanotube FET analysis.

Yamada, Toshishige↗
NASA NTRS1998

Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

Neudeck, Philip G.↗
NASA NTRS2004

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decision-making ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline (PANi) is an intriguing material because its electrical conductivity can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain, and when combined with polyethylene oxide (PEO), can be formed into nanofibers with diameters ranging from approximately 50 to 500 nm (depending on the deposition conditions). The initial goal of this work was to demonstrate transistor behavior in these nanofibers, thus creating a foundation for future logic devices.

Miranda, Felix A.↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS2016

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Transistor↗
NASA NTRS1981

Total-dose radiation effects data for semiconductor devices, volume 1

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. Data are presented by JPL for various NASA space programs on diodes, bipolar transistors, field effect transistors, silicon-controlled rectifiers, and optical devices. A vendor identification code list is included along with semiconductor device electrical parameter symbols and abbreviations.

Price, W. E.↗
NASA NTRS1982

Total-dose radiation effects data for semiconductor devices, volume 3

Volume 3 of this three-volume set provides a detailed analysis of the data in Volumes 1 and 2, most of which was generated for the Galileo Orbiter Program in support of NASA space programs. Volume 1 includes total ionizing dose radiation test data on diodes, bipolar transistors, field effect transistors, and miscellaneous discrete solid-state devices. Volume 2 includes similar data on integrated circuits and a few large-scale integrated circuits. The data of Volumes 1 and 2 are combined in graphic format in Volume 3 to provide a comparison of radiation sensitivities of devices of a given type and different manufacturer, a comparison of multiple tests for a single data code, a comparison of multiple tests for a single lot, and a comparison of radiation sensitivities vs time (date codes). All data were generated using a steady-state 2.5-MeV electron source (Dynamitron) or a Cobalt-60 gamma ray source. The data that compose Volume 3 represent 26 different device types, 224 tests, and a total of 1040 devices. A comparison of the effects of steady-state electrons and Cobat-60 gamma rays is also presented.

Price, W. E.↗
NASA NTRS1985

Total-dose radiation effects data for semiconductor devices: 1985 supplement, volume 1

Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.

Martin, K. E.↗