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New gated oscillator generates bursts of high-frequency sine waves, square waves, and triangular waves in response to control signals. Each burst starts at zero phase, with tight tolerances on signal amplitude and frequency. Frequencies in megahertz range are made possible by using high-speed comparators and high-speed flip-flop as fast-response threshold detector.
The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.
The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.
A technique for the redundant operation of counter modules is described. Redundant operation is maintained by detecting the zero state of each counter and clearing the other to that state, thus periodically resynchronizing the counters, and obtaining an output from both counters through AC coupled diode-OR gates. Redundant operation of counter flip flops is maintained in a similar manner, and synchronous operation of redundant squarewave clock generators of the feedback type is effected by connecting together the feedback inputs of the squarewave generators through a coupling resistor, and obtaining an output from both generators through AC coupled diode-OR gates.
The reported investigation shows that low-power TTL, standard TTL, low-power Schottky, and Schottky devices are all subject to upset by heavy ions. Low-power Schottky was the most sensitive of the device technologies tested. No evidence was found to correlate sensitivity to cosmic rays with any particular device manufacturer. The probability of upset of the logic devices is comparable to that of RAM's on a per-flip-flop basis, based on RAM data obtained by Kolasinski et al. (1979). The testing was performed by subjecting the devices to 120 MeV krypton ions from a cyclotron.
It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.
Numerical optical computing is discussed. A design for an optical pulse generator using a Hughes Liquid crystal light valve and intended for application as an optical clock in a numerical optical computer is considered. The pulse generator is similar in concept to the familiar electronic multivibrator, having a flip-flop and delay units.
A summary of single event upset data for 42 device types (including RAMs, 4-bit slices, microprocessors, 4-bit counters, and flip-flops) studied at 11 different accelerator tests (performed chiefly with the Berkeley 88-inch cyclotron and the Cal Tech Van de Graaff) is presented. All bipolar and NMOS RAMs were found to be SEU sensitive, some with very low LET thresholds. Some CMOS or CMOS/SOS RAMs were hard; and the CMOS microprocessors were hard, but the bipolar and NMOS microprocessors were soft. Several devices were found to exhibit a cross section that depends strongly on LET, even when the LET is well above the LET threshold. A ranking of hardness is presented for the logic devices tested.
The presence of high-energy protons in cosmic rays, solar flares, and trapped radiation belts around Jupiter poses a threat to the Galileo project. Results of a test of 10 device types (including 1K RAM, 4-bit microP sequencer, 4-bit slice, 9-bit data register, 4-bit shift register, octal flip-flop, and 4-bit counter) exposed to 590 MeV protons at the Swiss Institute of Nuclear Research are presented to clarify the picture of SEU response to the high-energy proton environment of Jupiter. It is concluded that the data obtained should remove the concern that nuclear reaction products generated by protons external to the device can cause significant alteration in the device SEU response. The data also show only modest increases in SEU cross section as proton energies are increased up to the upper limits of energy for both the terrestrial and Jovian trapped proton belts.
Circuit synchronizes clock and gate signals within one-quarter of clock cycle. Clock synchronizer with one-quarter-cycle skew constructed from three flip-flops, three NAND gates, and inverter. In addition gate signal to which clock synchronized, circuit requires square-wave input at twice desired clock frequency.
Circuit includes array of low-cost multivibrators. Inexpensive circuit converts frequency-modulated (FM) signal into digital signal. Consists of zero-crossing detector and series of monostable multivibrators and D-type flip-flops. Used to control filter.
The Flight Optimization System (FLOPS) is an aircraft configuration optimization program developed for use in conceptual design of new aircraft and in the assessment of the impact of advanced technology. The modular makeup of the program is illustrated. It contains modules for preliminary weights estimation, preliminary aerodynamics, detailed mission performance, takeoff and landing, and execution control. An optimization module is used to drive the overall design and in defining optimized profiles in the mission performance. Propulsion data, usually received from engine manufacturers, are used in both the mission performance and the takeoff and landing analyses. Although executed as a single in-core program, the modules are stored separately so that the user may select the appropriate modules (e.g., fighter weights versus transport weights) or leave out modules that are not needed.
A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.
Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.
Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.
The potential role of shock induced trailing edge separation (SITES) in limit cycle oscillations (LCO) was established. It was shown that the flip-flop characteristics of transition to and from SITES as well as its hysteresis could couple with wing modes with torsional motion and low damping. This connection led to the formulation of a very simple nonlinear math model using the linear equations of motion with a nonlinear step forcing function with hysteresis. A finite difference solution with time was developed and calculations were made for the F-111 TACT were used to determine the step forcing function due to SITES transition. Since no data were available for the hysteresis, a parameter study was conducted allowing the hysteresis effect to vary. Very small hysteresis effects, which were within expected bounds, were required to obtain reasonable response levels that essentially agreed with flight test results. Also in agreement with wind tunnel tests, LCO calculations for the 1/6 scale F-111 model showed that the model should have not experienced LCO.
The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.