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At least 127 records · Page 7

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DOE OSTI2014

The RAJA Portability Layer: Overview and Status

As computer architectures become increasingly complex and diverse, application developers face difficult challenges to achieve high performance while maintaining code portability. The problem is especially acute for large ASC multiphysics codes. Efficient parallel execution often requires tuning algorithms and data access to match processor and memory system constraints. Changing compiler directives and parallel programming model constructs on thousands of individual loops in a large code is disruptive and unwieldy. RAJA is a programming approach that we have been developing at Lawrence Livermore National Laboratory to encapsulate platform-specific concerns, related to both hardware and parallel programming models. The RAJA abstraction layer simplifies porting C/C++ codes to various programming models and architectures by reducing effort and developer disruption. In this report, we motivate and describe key aspects of RAJA. We also present a preliminary assessment of RAJA based on exploration in three ASC hydrodynamics codes at LLNL, which was one part of a three-part ASC Level 2 milestone, completed in September 2014.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Method for instruction sequence execution analysis and visualization

Various technologies pertaining to computer-executable instruction sequence forensics are described herein. In a general embodiment, an application development framework supports a function library that includes a plurality of recording functions. Calls to these functions are inserted into source code or bytecode of the computer-executable instruction sequence. The source code is then compiled, resulting in formation of instrumented machine code of the computer-executable instruction sequence. Alternately, the runtime environment interprets instrumented bytecode for the instruction sequence. A processor executes the machine code, and the called functions cause the processor to generate forensic data pertaining to portions of the computer-executable instruction sequence that correspond to locations in the source code where the calls were inserted. An execution instance of the computer-executable instruction sequence is visualized based upon the forensic data.

Sundermier, Amy↗

DOE OSTI2017

Method for monitoring/managing electrochemical energy device by detecting intercalation stage changes

A method for determining an operating state (e.g., state-of-charge or state-of-health) and/or generating management (charge/discharge) control information in a system including an electrochemical energy device (EED, e.g., a rechargeable Li-ion battery, supercapacitor or fuel cell) that uses optical sensors to detect the intercalation stage change events occurring in the EED. The externally or internally mounted optical sensors measure operating parameter (e.g., strain and/or temperature) changes of the EED during charge/recharge cycling, and transmit measured parameter data using light signals sent over optical fibers to a detector/converter. A processor then analyzes the measured parameter data, e.g., using a model-based estimation process, to detect intercalation stage changes (i.e., crystalline structure changes caused by migration of guest species, such as Li-ions, between the EED's anode and cathode), and generates the operating state and charge/discharge control information based the analysis.

25 ENERGY STORAGE↗

DOE OSTI2021

System and method of mapping topology

A system for determining a fingerprint of a structure is provided. The system includes a plurality of granules inserted in a structure having a plurality of fissures, fractures, and cracks (collectively apertures), each granule comprising a membrane, and at least one bubble of compressed gas formed in the membrane, the membrane selectively dissolving in presence of a predetermined fluid and thereby selectively bursting the at least one bubble, thereby generating a concussing vibration, at least at least i) three detection devices for two-dimensional mapping or ii) four detection devices for three-dimensional mapping placed proximate to the structure according to a predetermined placement schedule, and a computing device comprising a processor configured to receive data from the at least three or four detection devices and to determine location of the at least one bubble of each of the plurality of the granules at the time of bursting by triangulating the concussive vibration in order to determine location of the at least one bubble.

Pyrak-Nolte, Laura↗

DOE OSTI2022

System and method for remote detection and location of gas leaks

A system for monitoring for a gas leak from a gas containing structure is disclosed. The system includes a lens that directs an image of a scene of interest through an optical filter onto a detector. The filter is associated with the lens and the filter has one or more passbands that passes wavelengths which match one or more emission or reflectively wavelengths of the gas being monitored. A detector receives the image after the image passes through the lens and the filter. The detector generates image data representing the scene including the gas containing structure. A processor is configured to process the image data by executing machine executable code stored on a memory. The machine executable code processes the image data to identify turbulence flows in the image data such that turbulence flow indicates a gas leak, and generate and send an alert in response to the identification of a turbulence flow.

O'Neill, Mary D.↗

DOE OSTI2016

Data Movement in Data-Intensive High Performance Computing.

The cost of executing a floating point operation has been decreasing for decades at a much higher rate than that of moving data. Bandwidth and latency, two key metrics that determine the cost of moving data, have degraded significantly relative to processor cycle time and execution rate. Despite the limitation of sub-micron processor technology and the end of Dennard scaling, this trend will continue in the short-term making data movement a performance-limiting factor and an energy/power efficiency concern. Even more so in the context of large-scale and data-intensive systems and workloads. This chapter gives an overview of the aspects of moving data across a system, from the storage system to the computing system down to the node and processor level, with case study and contributions from researchers at the San Diego Supercomputer Center, the Oak Ridge National Laboratory, the Pacific Northwest National Laboratory, and the University of Delaware.

Data Movement↗

DOE OSTI2024

Nonlinear encoding in diffractive information processing using linear optical materials

Nonlinear encoding of optical information can be achieved using various forms of data representation. Here, we analyze the performances of different nonlinear information encoding strategies that can be employed in diffractive optical processors based on linear materials and shed light on their utility and performance gaps compared to the state-of-the-art digital deep neural networks. For a comprehensive evaluation, we used different datasets to compare the statistical inference performance of simpler-to-implement nonlinear encoding strategies that involve, e.g., phase encoding, against data repetition-based nonlinear encoding strategies. We show that data repetition within a diffractive volume (e.g., through an optical cavity or cascaded introduction of the input data) causes the loss of the universal linear transformation capability of a diffractive optical processor. Therefore, data repetition-based diffractive blocks cannot provide optical analogs to fully connected or convolutional layers commonly employed in digital neural networks. However, they can still be effectively trained for specific inference tasks and achieve enhanced accuracy, benefiting from the nonlinear encoding of the input information. Our results also reveal that phase encoding of input information without data repetition provides a simpler nonlinear encoding strategy with comparable statistical inference accuracy to data repetition-based diffractive processors. Our analyses and conclusions would be of broad interest to explore the push-pull relationship between linear material-based diffractive optical systems and nonlinear encoding strategies in visual information processors.

42 ENGINEERING↗

DOE OSTI2012

Advanced High-Speed 16-Bit Digitizer System

The fastest commercially available 16-bit ADC can only perform around 200 mega-samples per second (200 MS/s). Connecting ADC chips together in eight different time domains increases the quantity of samples taken by a factor of eight. This method of interleaving requires that the input signal being sampled is split into eight identical signals and arrives at each ADC chip at the same point in time. The splitting of the input signal is performed in the analog front end containing a wideband filter that impedance matches the input signal to the ADC chips. Each ADC uses a clock to tell it when to perform a conversion. Using eight unique clocks spaced in 45-degree increments is the method used to time shift when each ADC chip performs its conversion. Given that this control clock is a fixed frequency, the clock phase shifting is accomplished by tightly controlling the distance that the clock must travel, resulting in a time delay. The interleaved ADC chips will now generate digital data in eight different time domains. These data are processed inside a field-programmable gate array (FPGA) to move the data back into a single time domain and store it into memory. The FPGA also contains a Nios II processor that provides system control and data retrieval via Ethernet.

42 ENGINEERING↗

DOE OSTI2015

Scalable and efficient algorithms for the propagation of uncertainty from data through inference to prediction for large-scale problems, with application to flow of the Antarctic ice sheet

The majority of research on efficient and scalable algorithms in computational science and engineering has focused on the forward problem : given parameter inputs, solve the governing equations to determine output quantities of interest. In contrast, in this paper, we consider the broader question: given a (large-scale) model containing uncertain parameters, (possibly) noisy observational data, and a prediction quantity of interest, how do we construct efficient and scalable algorithms to (1) infer the model parameters from the data (the deterministic inverse problem ), (2) quantify the uncertainty in the inferred parameters (the Bayesian inference problem), and (3) propagate the resulting uncertain parameters through the model to issue predictions with quantified uncertainties (the forward uncertainty propagation problem )? We present efficient and scalable algorithms for this end-to-end, data-to-prediction process under the Gaussian approximation and in the context of modeling the flow of the Antarctic ice sheet and its effect on loss of grounded ice to the ocean. The ice is modeled as a viscous, incompressible, creeping, shear-thinning fluid. The observational data come from satellite measurements of surface ice flow velocity, and the uncertain parameter field to be inferred is the basal sliding parameter, represented by a heterogeneous coefficient in a Robin boundary condition at the base of the ice sheet. The prediction quantity of interest is the present-day ice mass flux from the Antarctic continent to the ocean. We show that the work required for executing this data-to-prediction process—measured in number of forward (and adjoint) ice sheet model solves—is independent of the state dimension, parameter dimension, data dimension, and the number of processor cores. The key to achieving this dimension independence is to exploit the fact that, despite their large size, the observational data typically provide only sparse information on model parameters. This property can be exploited to construct a low rank approximation of the linearized parameter-to-observable map via randomized SVD methods and adjoint-based actions of Hessians of the data misfit functional.

54 ENVIRONMENTAL SCIENCES↗

DOE OSTI2013

Distributed merge trees

Improved simulations and sensors are producing datasets whose increasing complexity exhausts our ability to visualize and comprehend them directly. To cope with this problem, we can detect and extract significant features in the data and use them as the basis for subsequent analysis. Topological methods are valuable in this context because they provide robust and general feature definitions. As the growth of serial computational power has stalled, data analysis is becoming increasingly dependent on massively parallel machines. To satisfy the computational demand created by complex datasets, algorithms need to effectively utilize these computer architectures. The main strength of topological methods, their emphasis on global information, turns into an obstacle during parallelization. We present two approaches to alleviate this problem. We develop a distributed representation of the merge tree that avoids computing the global tree on a single processor and lets us parallelize subsequent queries. To account for the increasing number of cores per processor, we develop a new data structure that lets us take advantage of multiple shared-memory cores to parallelize the work on a single node. Finally, we present experiments that illustrate the strengths of our approach as well as help identify future challenges. Copyright © 2013 ACM 978-1-4503-1922-5/13/ 02...$15.00.

Morozov, D↗

DOE OSTI2013

Distributed Merge Trees

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Systems and methods for plane-wave and fan-beam ultrasound-waveform tomography

A method for plane-wave or fan-beam ultrasound tomography includes: controlling, by a processor, a multi-channel ultrasound array controller to control a linear ultrasound transducer array to emit plane-wave or fan-beam ultrasound into a biological tissue, the linear ultrasound transducer array including a plurality of transducers; receiving, by the processor, plane-wave or fan-beam ultrasound waveform data from the transducers, the plane-wave or fan-beam ultrasound waveform data including reflections of the plane-wave or fan-beam ultrasound from the biological tissue; computing, by the processor, a synthetic ultrasound-waveform inversion from the received plane-wave or fan-beam ultrasound waveform data; and computing, by the processor, an image of the biological tissue from the synthetic ultrasound-waveform inversion.

Huang, Lianjie↗

DOE OSTI2014

Lattice QCD with Domain Decomposition on Intel Xeon Phi Co-Processors

The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromodynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel Xeon Phi co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

Heybrock, Simon↗

DOE OSTI2017

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” and if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Power system disturbance location determination based on rate of change of frequency

A method for determining a location of a disturbance in a power system is provided. The method includes receiving data from a plurality of sensors distributed across the power system; determining, with one or more processors, for each sensor, an extremum of the data corresponding to the sensor; interpolating, with the one or more processors, the extrema; and presenting, on one or more display units, a location corresponding to a global maximum of the interpolated extrema as the location of the disturbance. The method may further include, if a difference between the largest extremum and each of remaining extremum is greater than a predetermined threshold, skipping the interpolating step and the presenting step, and presenting a location of the sensor corresponding to the largest extremum as the location of the disturbance.

You, Shutang↗

DOE OSTI2024

Reducing measurement costs by recycling the Hessian in adaptive variational quantum algorithms

Abstract Adaptive protocols enable the construction of more efficient state preparation circuits in variational quantum algorithms (VQAs) by utilizing data obtained from the quantum processor during the execution of the algorithm. This idea originated with Adaptive Derivative-Assembled Problem-Tailored variational quantum eigensolver (ADAPT-VQE), an algorithm that iteratively grows the state preparation circuit operator by operator, with each new operator accompanied by a new variational parameter, and where all parameters acquired thus far are optimized in each iteration. In ADAPT-VQE and other adaptive VQAs that followed it, it has been shown that initializing parameters to their optimal values from the previous iteration speeds up convergence and avoids shallow local traps in the parameter landscape. However, no other data from the optimization performed at one iteration is carried over to the next. In this work, we propose an improved quasi-Newton optimization protocol specifically tailored to adaptive VQAs. The distinctive feature in our proposal is that approximate second derivatives of the cost function are recycled across iterations in addition to optimal parameter values. We implement a quasi-Newton optimizer where an approximation to the inverse Hessian matrix is continuously built and grown across the iterations of an adaptive VQA. The resulting algorithm has the flavor of a continuous optimization where the dimension of the search space is augmented when the gradient norm falls below a given threshold. We show that this inter-optimization exchange of second-order information leads the approximate Hessian in the state of the optimizer to be consistently closer to the exact Hessian. As a result, our method achieves a superlinear convergence rate even in situations where the typical implementation of a quasi-Newton optimizer converges only linearly. Our protocol decreases the measurement costs in implementing adaptive VQAs on quantum hardware as well as the runtime of their classical simulation.

Ramôa, Mafalda (ORCID:0000000302187801)↗

DOE OSTI2019

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.

97 MATHEMATICS AND COMPUTING↗