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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits

A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

Buehler, Martin G.↗
DOE OSTI2018

Defect screening method for electronic circuits and circuit components using power spectrum anaylysis

A method involving the non-destructive testing of a sample electrical or electronic device is provided. The method includes measuring a power spectrum of the device and performing a Principal Component Analysis on the power spectrum, thereby to obtain a set of principal components of the power spectrum. The method further includes selecting a subset consisting of some of the principal components, and comparing the subset to stored reference data that include representations in terms of principal components of one or more reference populations of devices. Based at least partly on the comparison, the sample device is classified relative to the reference populations.

Tangyunyong, Paiboon↗
DOE OSTI2021

Dimming LED circuit augmenting DC/DC controller integrated circuit

Embodiments include systems, methods, and apparatuses for providing a dimming function in a single stage AC input light emitting diode (LED) driver with a controller that contains an on-chip error amplifier and an on-chip fixed reference voltage source coupled to a first input of the error amplifier. The controller controls a duty cycle of a switching transistor to cause a feedback voltage, applied to a first package input terminal, to match the reference voltage. To achieve a dimming function, a voltage across a current sense resistor in series with the LEDs is applied to a first input of a high gain differential amplifier, and a variable dimming control voltage is applied to a second input of the differential amplifier. The output of the differential amplifier is coupled to the first package input terminal. The differential amplifier input signals will be matched at the target LED current level.

Song, Zhengrong↗
DOE OSTI2026

Towards Generalizable and Efficient Circuit Topology Design: A Graph-Transformer-based Surrogate Model with Curriculum Learning

Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.

Lu, Haoshu [New Jersey Institute of Technology (NJ↗
DOE OSTI2021

Reoptimization of Quantum Circuits via Hierarchical Synthesis

The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations to achieve higher circuit fidelity. Further, using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2013

Investigating Short Circuit Models for Wind Turbine Generators

Short circuit study needs to be performed at the planning stage before connecting large gen erators with the electric grid. This study will reveal the impact of new generation on the fault levels of the grid. The fault levels will determine the rating of nearby equipment and setting of relays. However, a short circuit model of the new generation is required for this study. This report investigates and quantifies the short circuit models of different wind turbine generators (WTGs) and of wind farms, and using these models, explores the effects of the wind farms on the nearby switchgear. WTGs, commonly classified as Type 1, Type 2, Type 3, and Type 4, exhibit different short circuit behavior depending upon their architecture and controls. The short circuit model (synonymous to Thevenin model) of Type 1 WTG is well known; it comprises of a voltage source behind a transient reactance, X'. The transient reactance X' is derived using the reactance of stator, rotor and the magnetizing reactance. In case of Type 2 WTG, an external rotor resistance is used to increase the range of operating slips. The value of the external rotor resistance increases at higher operating slips. The effect of the external rotor resistance on the fault current response is analyzed by simulating a validated model of Type 2 WTG. The validation is performed using the field data from an actual 67-machine Type 2 wind farm located in Wyoming, USA. The results shows that the external rotor resistance should be considered in its Thevenin impedance for better accuracy. A wind farm contains a large number of WTGs, pad mounted transformers, and cables typically connected in a ‘daisy chain” configuration. The effect of these cable impedances on the short circuit model of Type 2 wind farm is examined using the validated models. It is found that the collector circuit cables inside the farm do not have a significant effect on the short circuit model of the farm. Based on this finding, a simple equivalencing procedure for the wind farm is proposed and validated. Faults inside and outside the wind farm are analyzed and recommendations to select main circuit breakers and generator circuit breakers are made. Type 3 WTG, also known as Doubly Fed Asynchronous Generator (DFAG), uses back to back converters in the rotor circuit to inject slip frequency voltage into the rotor circuit. Until recently, these machines used crowbar to short the rotor circuit during faults to protect the converter com ponents form high rotor currents resulting from faults. This type of WTG is simulated and the model is validated using field data from a 66-machine Type 3 wind farm in Wyoming, USA. The simulation study reveals that the crowbar feature is activated almost immediately after the fault takes place, and remains activated throughout the fault-period. This confirms that the short circuit model for Type 3 WTG with crowbar is similar to the model for Type 2 WTG. In the past, wind farms were allowed to disconnect during faults. However, recent grid codes around the world and in the United States demand that the wind farms be kept connected to the grid during faults, and provide certain reactive power quantified based on the voltage dip at the point of interconnection. This requirement, also called low voltage ride through (LVRT), can be accomplished by using Type 4 WTGs that employ full back to back converter interface between generators (permanent magnet synchronous generators are typically used) and the grid. However, the controls are proprietary, and hence the short circuit models are not well defined. This report proposes controls that enable the WTG to comply with the strictest grid codes, and based on this model, proposes a short circuit model of the Type 4 WTG. This model is not validated due to lack of validation data, but the use of grid code requirements as control objectives lends good credibility to the model. PSCAD/EMTDC ® , a powerful and time-tested time-domain simulation software is used to implement all models. This software is capable of modeling in detail all components of wind farms, and all components and controls of converters in time domain.

17 WIND ENERGY↗
DOE OSTI2021

Pilot-Scale Testing of an Integrated Circuit for the Extraction of Rare Earth Minerals and Elements from Coal and Coal Byproducts Using Advanced Separation Technologies

The primary objective of this project was to develop and demonstrate an integrated pilot-scale circuitry for recovering high-value rare earth elements (REEs) from coal and coal byproducts. The target performance was to produce a mixed REE product with content of at least two percent by weight on a dry mass basis in a cost-effective and environmentally benign manner. During the first nine months of the project period (Phase 2 Budget Period 2), pilot plant construction was completed including all field site startup activities such as permitting, engineering design, procurement/bidding, unit fabrication, site construction, equipment installation, module assembly, safety training, and circuit shakedown. During the remaining 21 months of project period (Phase 2 Budget Period 3), detailed field-testing activities were performed including feedstock sample collection and preparation, exploratory testing, circuit modification, detailed parametric study, and performance optimization. A detailed techno-economic analysis was performed based on the pilot plant testing findings which provided various scenarios for REE production. The project successfully accomplished the proposed target performance by producing mixed rare earth oxide (REO) with greater than 90% purity by weight in a continuous pilot scale operation from two distinctly different coarse refuse materials (i.e., West Kentucky No. 13 and Fire Clay coal seams), and at least three secondary sources (i.e., heap leach process and naturally formed acid mine drainage system). Project partners included the University of Kentucky, Virginia Tech, West Virginia University, Alliance Coal, Blackhawk Mining, Mineral Refining Company, and Mineral Separation Technologies. The pilot scale test facility was constructed at a former mining complex owned by Alliance Natural Resource Partners (Alliance Coal). The site was rehabilitated to accommodate the equipment installation, construction and fabrication, electrical power requirement, water line management and containment. The process units constructed and installed included X-ray sorting unit, crushing and grinding unit, physical separation unit, acid leaching unit, solvent extraction unit, and wastewater management unit. A rare earth mineral concentration unit was constructed as a standalone unit for flexible operation. A detailed environmental assessment and control plan was carried out to identify and quantify any potential impacts of the pilot-scale processing circuitry on the human and eco-system health and well-being. Corresponding mitigation strategies and control measures were provided. A conceptual flowsheet was developed to effectively remove thorium and uranium from high purity rare earth oxide mix or any potential radionuclide enriched stream. The two distinct feedstock materials were secured from the Blackhawk Mining Complex in eastern Kentucky where the Fire Clay (Hazard No. 4) seam is processed. The West Kentucky No. 13 (Baker) coarse refuse material was collected from an active process stream at an Alliance coal preparation plant located in western Kentucky. Characterization analysis indicated that both of feed materials generated from the two sources contained >300 ppm of TREEs on a dry whole mass basis which met the requirements for a qualified feed stock. The two feedstocks were further upgraded using a dual x-ray sorter to prepare the feed material for hydrometallurgical circuit. Thermal treatment on feed material prior to leaching was found to: 1) improve the leaching recovery of REEs, 2) increase the leaching kinetics, and 3) allow the leaching reaction to occur at lower acidity. Roasting at 600°C was selected as the pre-treatment condition for both West Kentucky No. 13 and Fire Clay coarse refuse material. Over 40% of leaching recovery was achieved by roasting West Kentucky No. 13 material having a top particle size of 3 mm in the pilot scale operation using 1.2M sulfuric acid leaching at 75OC. Initial pilot scale testing involved continuous operation of the pilot plant for 94 hours. The leaching unit was operated at solid-to-liquid ratio of 1 to 10 (w/v) using 0.5M sulfuric acid solution at a temperature of 75°C. The continuous solvent extraction circuit utilized rougher and cleaner units with DEHPA and TBP as the extractants. An innovative stripping circuit was developed to accumulate the REE concentration in the stripping solution to a level above 600 ppm. A bleed stream from the recycled strip solution was treated using oxalic acid precipitation which produced a high grade rare earth oxalate. The oxalate product was roasted to remove the oxalate which produced a rare earth oxide product having a purity greater 90%. Due to high concentrations of contaminant ions in the pregnant leach solution (PLS), a modified flowsheet was developed that involved pre-concentration of the REEs using multiple stages of precipitation and redissolution. The advantage of this process was improved removal of contamination before the downstream purification process and a significant cost reduction relative to the circuit that utilized the solvent extraction process. The modified circuitry included processes involving leaching, multistage precipitation, redissolution, and oxalate precipitation followed by roasting of the oxalate product. The circuit produced a mixed REO that was 92.96% pure from the initial test. A detailed parametric test plan was carried out which involved varying key parameters including solids feed rate, acid flowrate, acid concentration, multistage precipitation pH, redissolution pH, oxalate precipitation dosage and pH. The response variables included REE recovery, contaminant recovery, REO product grade and overall chemical consumption. Test results indicated that the acid-to-solid ratio is the key parameter to leaching efficiency as performance deteriorated with an increase in solids concentration. The optimal pH determined for REE precipitation and redissolution was 6.5 and 2.5, respectively. Additional tests were conducted to further improve the flowsheet. Recirculating a portion of the PLS to the feed of the leach tanks improved the leaching performance by lowering the pH of the leaching system and reducing the contamination recovery by shortening the residence time. Moreover, the removal of Al prior to REE precipitation significantly reduced the oxalic acid consumption in the oxalate precipitation circuit. The modified circuit produced over 90% grade REO by weight from both West Kentucky No. 13 and Fire Clay coarse refuse material in pilot scale continuous test programs. A case analysis model was developed to project the REE and major contaminants concentration in each PLS stream based on the leaching condition, pH cut point, and oxalic acid dosage. A correlation was established using empirical and semi-empirical models. Using the models, chemical consumption required for each stage was predicted based on the projected performance of the hydrometallurgy circuit. After identifying the optimum conditions, validation tests were carried out for the treatment of both West Kentucky No. 13 and Fire Clay coarse refuse materials in the pilot plant. The actual circuit performance and chemical consumptions were very close to the model predictions. Other than the two coarse refuse sources, several secondary feedstocks were also tested in the pilot plant facility. A “heap leach” system was constructed using the coarse refuse material generated from cleaning the West Kentucky No. 13 seam coal. Using the two stage SX rougher and cleaner circuit, a concentrate with a grade >90% REO was produced while recovering >97% of the REEs from the heap leach PLS. Naturally generated acid mine drainage (AMD) from West Kentucky No.13 mine was processed using the multistage precipitation circuit in the pilot plant in a test conducted for a period of 32 hours. The final grade of the mix RE oxide produced from the AMD was 90.84% with an overall circuit recovery of 64%. The primary source of REE was the selective precipitation steps involving iron and aluminum rejection. The hydrophobic-hydrophilic separation (HHS) process was proven to effectively recover coal from fine waste materials. For REM recovery, the HHS process was able to produce concentrates at grades of approximately 1.8% REE on an ash basis; however, recovery values were typically low, <10%, under the optimal conditions determined in the laboratory-scale testing. Staged testing of the pilot-scale HHS process for coal recovery and semi-continuous laboratory testing for REM testing showed that a total concentration ratio of more than 15x was observed for the REM recovery process. A circuit simulation package was developed for REE extraction and purification using a spreadsheet-based platform (Microsoft Excel). The REESim circuit simulation package is configured to track the mass and volume flows of components passing through a series of unit operations specified and configured by the user. The mass rates can then be utilized by the user to determine important performance indicators such as product mass yields, concentrate purity levels, element-by-element recoveries, and so forth. The techno-economic analysis showed that the roasting and leaching operations were the most expensive capital items, each contributing approximately 30% to the total capital cost. One notable contributor to the high production costs was the low REE recovery observed in the pilot scale trials. The product basket price was shown to have a strong influence on the economic viability of the scenarios, with the scandium price being the most significant influencer. Operating cost was shown to be extremely sensitive to REE recovery, REE feed grade, and leaching acid consumption. An analysis of ten different scenarios for a 500 t/h commercial operation revealed that three were economically favorable, producing internal rates of return varying from 27.7% to 33.1% and payback periods of 4 to 5 years. The project successfully developed and demonstrated a process to recover REEs from coal and coal byproducts in a pilot-plant operation which consistently produced over 90% grade REO mix from varies types of feedstocks. Commercialization analysis showed that the technology readiness level successfully achieved TRL 6 at the end of the project and demonstrated the need and the potential for scaling the process to further advance the technologies toward the goal of providing a domestic supply of REEs at a commercial scale.

01 COAL, LIGNITE, AND PEAT↗
DOE OSTI2012

Universal programmable quantum circuit schemes to emulate an operator

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2017

Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth

Quantum circuits for basic mathematical functions such as division are required to implement scientific computing algorithms on quantum computers. In this work, we propose two designs for quantum integer division. The designs are based on quantum Clifford+T gates and are optimized for T-count and T-depth. Quantum circuits that are based on Clifford+T gates can be made fault tolerant in nature but the T gate is very costly to implement. As a result, reducing T-count and T-depth have become important optimization goals. Existing quantum hardware is limited in terms of number of available qubits. Thus, ancillary qubits are a circuit overhead that needs to be kept to a minimum. We propose two quantum integer division circuits. The first quantum integer division circuit is based on the non-restoring division algorithm. The proposed non-restoring division circuit is optimized for total quantum hardware (T-count and T-depth) cost but requires 2* n + 1 ancillary qubits. We also propose a quantum integer division circuit based on the restoring division algorithm. The proposed restoring division circuit is optimized for total qubits. The design requires only n ancillary qubits but will need more quantum hardware than the non-restoring division circuit. Both proposed quantum circuits are based on (i) a new quantum conditional addition circuit, (ii) a new quantum adder-subtractor and (iii) a new quantum subtraction circuit. Further, both designs are compared and shown to be superior to existing work in terms of T-count and T-depth. The proposed quantum non-restoring integer division circuit has a 96% improvement in terms of T-count and a 93% improvement in terms of T-depth compared to existing work. The proposed quantum restoring integer division circuit has a 91% improvement in terms of T-count and a 86% improvement in terms of T-count compared to the existing work.

Thapliyal, Himanshu↗
NASA NTRS2006

Submicrosecond Power-Switching Test Circuit

A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a repetitive waveform from a signal generator, momentary closure of a push-button switch, or closure or opening of a manually operated on/off switch. In the case of a signal generator, one can adjust the frequency and duty cycle as needed to obtain the desired AC power-supply response, which one could display on an oscilloscope. Momentary switch closure could be useful for obtaining (and, if desired, displaying on an oscilloscope set to trigger on an event) the response of a power supply to a single load transient. The on/off switch can be used to switch between load states in which static-load regulation measurements are performed.

Folk, Eric N.↗
NASA NTRS2022

Space Induced Discharge Model to Be Used on Interface Circuit Vulnerability Assessment

Charging can occur in space due to plasma and high energy particles. Charging is especially severe in certain earth orbits such as geostationary orbit, medium earth orbit and highly inclined orbit. A spacecraft that travels to other planets such as Jupiter also encounters high level of charging due to Jupiter’s radiation belt. The major concern for spacecraft operation due to charging is the survival of sensitive electrical circuits. Dielectrics and floating metal can charge up and discharge onto interface circuits. The electrical circuits need to be evaluated for survival from the electrostatic-discharge (ESD) threat. Both ESD induced upset and damage need to be assessed. The interface circuits are often located inside a shielded unit in the spacecraft structure or a shielded vault with sufficient radiation shielding to avoid surface and internal charging. The materials external to the highly shielded area can charge up and discharge onto wires that can directly dissipate the ESD onto the interface circuits. Figure 1 shows a possible discharge mechanism onto the interfacing circuits. If the wire has an external shield or a coaxial line, some or most of the discharge can flow on the shield to chassis ground. There is always coupling from external discharge. If the wire has no shield, the discharge flows onto the interface circuit. Fig. 1 Possible discharge paths onto the interface circuits. The purpose of this article is to address how to model the ESD threat to be used as the discharge source onto the interface circuit based on the electron beam test data. Different models are needed for different impedances associated with the interface circuits. Once those models are derived, one needs to analyze the interface circuit with the corresponding model using an electrical simulation tool. Then, the circuit’s front-end components can be assessed for damage and upset. Upset is highly dependent on the circuit operation and system requirements, and thus it is not addressed any further. Damage of electrical parts is often rated under Human-Body-Model (HBM) ESD. One can utilize this industry-wide available information to assess the damage vulnerability due to space discharges. However, the HBM waveform does not always match the discharge waveform. To estimate the damage vulnerability of the circuit and set margin, one needs to compare the equivalent energy delivered to the victim between a HBM discharge and the results from an ESD source model based on actual discharges. This paper presents such a comparison for a few select cases.

Xie, Julie↗