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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Anti-symmetric barron functions and their approximation with sums of determinants

A fundamental problem in quantum physics is to encode functions that are completely anti-symmetric under permutations of identical particles. The architecture of neural network models for the electron wave function typically comprises an equivariant component followed by a summation of determinants. The recently introduced Generic Antisymmetric (GA) block is designed to enhance the expressivity of such neural wave functions, and it was found that the 2-layer GA block achieved more accurate energies than the corresponding single-determinant FermiNet architecure, suggesting its promise as a way to improve the expressivity of neural wave functions. In this paper we show how the function expressed by the 2-layer GA block can be decomposed into a sum of determinants. We formalize this result by defining the antisymmetric Barron space as a generalized version of the 2-layer GA block and providing an appromation theorem for this function class. This result can be viewed as a negative result showing that the 2-layer GA block is not more expressive than using multiple determinants.

Abrahamsen, Nilin↗
NASA NTRS1999

High-Performance, Low-Complexity Codes Researched for Communication Channels

NASA Lewis Research Center s Communications Technology Division has an ongoing program in the development of efficient channel coding schemes for satellite communications applications. Through a university grant, as a part of this research, the University of Toledo is investigating the performance of turbocodes, which use parallel concatenation of non-systematic convolutional encoders with an interleaver. The error correcting capacity of these codes is close to the Shannon limit. The research emphasis is on the development of low-complexity, but higher rate (greater than one half), turbocodes and on the iterative decoding of block codes.

Kwatra, Subhash C.↗
NASA NTRS2021

A Distributed Approach to High-Rate Delay Tolerant Networking Within a Virtualized Environment

The High-Rate Delay Tolerant Networking (HDTN) project has taken a distributed service-based approach to the development of a highly efficient delay tolerant networking (DTN) implementation. Through the analysis of many DTN implementations, system and mission requirements as well as the DTN protocol specifications, HDTN has worked to infuse modern computing technologies into the NASA approach to interplanetary networking. The initial use case of the HDTN software runs on a hypervisor representative of the International Space Station (ISS) DTN Gateway. In this scenario, multiple emulated payloads will send science data through HDTN to a mission operations center. HDTN will provide store and forward capability as well as network flow management. This paper discusses the infusion path of cognitive networking technologies in the NASA SCaN networks using the DTN architecture and protocols as the basis for cognitive routing and network management capabilities. HDTN has been developing the Bundle Protocol encoding and decoding mechanisms and messaging framework that can be used as the basis for integrating DTN with various learning and decision-making processes. The concepts of distributed computing, network virtualization, software defined networking and delay tolerant networking are basic building blocks which will further the development of cognitive networking. In addition to discussion of the HDTN software development and testing, this paper examines the role that each of these technologies play in the evolution of the current state of space networking into an intelligent network of networks.

Delay Tolerant Networking↗
NASA NTRSDate not supplied

A Distributed Approach to High-Rate Delay Tolerant Networking Within a Virtualized Environment

The High-Rate Delay Tolerant Networking (HDTN) project has taken a distributed service-based approach to the development of a highly efficient delay tolerant networking (DTN) implementation. Through the analysis of many DTN implementations, system and mission requirements as well as the DTN protocol specifications, HDTN has worked to infuse modern computing technologies into the NASA approach to interplanetary networking. The initial use case of the HDTN software runs on a hypervisor representative of the International Space Station (ISS) DTN Gateway. In this scenario, multiple emulated payloads will send science data through HDTN to a mission operations center. HDTN will provide store and forward capability as well as network flow management. This paper discusses the infusion path of cognitive networking technologies in the NASA Space Communications and Navigation (SCaN) networks using the DTN architecture and protocols as the basis for cognitive routing and network management capabilities. HDTN has been developing the Bundle Protocol encoding and decoding mechanisms and messaging framework that can be used as the basis for integrating DTN with various learning and decision-making processes. The concepts of distributed computing, network virtualization, software defined networking and delay tolerant networking are basic building blocks which will further the development of cognitive networking. In addition to discussion of the HDTN software development and testing, this paper examines the role that each of these technologies play in the evolution of the current state of space networking into an intelligent network of networks.

Rachel Mary Dudukovich↗
NASA NTRS2004

User-Friendly Interface Developed for a Web-Based Service for SpaceCAL Emulations

A team at the NASA Glenn Research Center is developing a Space Communications Architecture Laboratory (SpaceCAL) for protocol development activities for coordinated satellite missions. SpaceCAL will provide a multiuser, distributed system to emulate space-based Internet architectures, backbone networks, formation clusters, and constellations. As part of a new effort in 2003, building blocks are being defined for an open distributed system to make the satellite emulation test bed accessible through an Internet connection. The first step in creating a Web-based service to control the emulation remotely is providing a user-friendly interface for encoding the data into a well-formed and complete Extensible Markup Language (XML) document. XML provides coding that allows data to be transferred between dissimilar systems. Scenario specifications include control parameters, network routes, interface bandwidths, delay, and bit error rate. Specifications for all satellite, instruments, and ground stations in a given scenario are also included in the XML document. For the SpaceCAL emulation, the XML document can be created using XForms, a Webbased forms language for data collection. Contrary to older forms technology, the interactive user interface makes the science prevalent, not the data representation. Required versus optional input fields, default values, automatic calculations, data validation, and reuse will help researchers quickly and accurately define missions. XForms can apply any XML schema defined for the test mission to validate data before forwarding it to the emulation facility. New instrument definitions, facilities, and mission types can be added to the existing schema. The first prototype user interface incorporates components for interactive input and form processing. Internet address, data rate, and the location of the facility are implemented with basic form controls with default values provided for convenience and efficiency using basic XForms operations. Because different emulation scenarios will vary widely in their component structure, more complex operations are used to add and delete facilities.

Liszka, Kathy J.↗
NASA NTRSDate not supplied

Flexible Data and Frame Synchronization Structure for the LunaNet PNT Signal

A LunaNet Lunar Augmented Navigation Service (LANS) is being developed to enable a position, navigation, and timing service for future Lunar operations. The signal includes two components. An in-phase data channel signal is spread by a 1.023 MCPS ranging code that provides a high-rate data message at 250 bps and is encoded by a strong Low Density Parity Check (LDPC) code. A pilot channel with a 5.115 MCPS spreading code is also provided. The pilot code is configured with a secondary (overlay) code that does not currently provide absolute time or frame Synchronization as is the case for L1C. This work shows the advantage of implementing an overlay structure that provides absolute time for the LunaNet LANS signal structure known as the Augmented Forward Signal (AFS). The LunaNet AFS structure was developed to service two classes of user receivers. The first class is a low-complexity user receiver that only receives the 1.023 MCPS signal and does not use the 5.115 MCPS pilot channel. For this class of user, a data frame Sync word is needed. The second class of receiver is a high-end receiver that can processes both data and pilot channels to take advantage of the higher chip rate pilot channel for enhanced robustness and improved accuracy. In the current draft LunaNet LANS AFS design, these users must employ the frame Sync word in the data channel and obtain absolute time after decoding the AFS navigation message. The signal structure would greatly benefit from the addition of a pilot overlay structure that provides absolute time and robust frame Sync for high-end users as done for L1C. To provide a more robust and interoperable AFS structure, this work summarizes a study and recommends alternatives for a new overlay code on the pilot channel that provides absolute time and a Sync word approach on the data channel. The overlay code and Sync word are designed to allow for flexible and robust data synchronization for both low- complexity and high-end user receivers. The new overlay code structure permits frame synchronization performance that is as good as or better than the L1 C signal, while enabling a determination of absolute time upon frame Sync to aid high-end assisted LANS AFS user receivers at low signal to noise levels. We also present the design of rate-matched 5G new radio (5GNR) LDPC codes that fit within the current 6000-symbol frame size along with a time of interval (TOI) word, frame ID (FID) word, and the remaining LunaNet AFS data message blocks. The paper describes and demonstrates robust frame Synchronization performance of the overlay code and Synch word approaches. The results are described in terms of probability of missed detection and probability of false alarm for a correct frame Synchronization at low Eb/No levels expected for decoding the TOI word and LDPC encoded data. Advantages of the proposed data Synchronization structure will be described along with use cases for low-end and high-end receivers. Practical implementation considerations will also be described.

LunaNet↗
NASA NTRSDate not supplied

Flexible Data and Frame Synchronization Structure for the LunaNet PNT Signal

A LunaNet Lunar Augmented Navigation Service (LANS) is being developed to enable a position, navigation, and timing service for future Lunar operations [1]. The signal includes two components. An in-phase data channel signal is spread by a 1.023 MCPS ranging code that provides a high-rate data message at 250 bps and is encoded by a strong Low Density Parity Check (LDPC) code. A pilot channel with a 5.115 MCPS spreading code is also provided. The pilot code is configured with a secondary (overlay) code that does not currently provide absolute time or frame Synchronization as is the case for L1C [2] [3]. This work shows the advantage of implementing an overlay structure that provides absolute time for the LunaNet LANS signal structure known as the Augmented Forward Signal (AFS). The LunaNet AFS structure was developed to service two classes of user receivers. The first class is a low-complexity user receiver that only receives the 1.023 MCPS signal and does not use the 5.115 MCPS pilot channel. For this class of user, a data frame Sync word is needed. The second class of receiver is a high-end receiver that can processes both data and pilot channels to take advantage of the higher chip rate pilot channel for enhanced robustness and improved accuracy. In the current draft LunaNet LANS AFS design, these users must employ the frame Sync word in the data channel and obtain absolute time after decoding the AFS navigation message [2]. The signal structure would greatly benefit from the addition of a pilot overlay structure that provides absolute time and robust frame Sync for high-end users as done for L1C [3]. To provide a more robust and interoperable AFS structure, this work summarizes a study and recommends alternatives for a new overlay code on the pilot channel that provides absolute time and a Sync word approach on the data channel. The overlay code and Sync word are designed to allow for flexible and robust data synchronization for both low- complexity and high-end user receivers. The new overlay code structure permits frame synchronization performance that is as good as or better than the L1 C signal, while enabling a determination of absolute time upon frame Sync to aid high-end assisted LANS AFS user receivers at low signal to noise levels. We also present the design of rate-matched 5G new radio (5GNR) LDPC codes that fit within the current 6000-symbol frame size along with a time of interval (TOI) word, frame ID (FID) word, and the remaining LunaNet AFS data message blocks. The paper describes and demonstrates robust frame Synchronization performance of the overlay code and Synch word approaches. The results are described in terms of probability of missed detection and probability of false alarm for a correct frame Synchronization at low Eb/No levels expected for decoding the TOI word and LDPC encoded data. Advantages of the proposed data Synchronization structure will be described along with use cases for low-end and high-end receivers. Practical implementation considerations will also be described.

Philip Dafesh↗
NASA NTRS1984

Memory-based parallel data output controller

A memory-based parallel data output controller employs associative memories and memory mapping to decommutate multiple channels of telemetry data. The output controller contains a random access memory (RAM) which has at least as many address locations as there are channels. A word counter addresses the RAM which provides as it outputs an encoded peripheral device number and a MSB/LSB-first flag. The encoded device number and a bit counter address a second RAM which contains START and STOP flags to pick out the required bits from the specified word number. The LSB/MSB, START and STOP flags, along with the serial input digital data go to a control block which selectively fills a shift register used to drive the parallel data output bus.

Stattel, R. J.↗
NASA NTRS1994

Low-complexity wavelet filter design for image compression

Image compression algorithms based on the wavelet transform are an increasingly attractive and flexible alternative to other algorithms based on block orthogonal transforms. While the design of orthogonal wavelet filters has been studied in significant depth, the design of nonorthogonal wavelet filters, such as linear-phase (LP) filters, has not yet reached that point. Of particular interest are wavelet transforms with low complexity at the encoder. In this article, we present known and new parameterizations of the two families of LP perfect reconstruction (PR) filters. The first family is that of all PR LP filters with finite impulse response (FIR), with equal complexity at the encoder and decoder. The second family is one of LP PR filters, which are FIR at the encoder and infinite impulse response (IIR) at the decoder, i.e., with controllable encoder complexity. These parameterizations are used to optimize the subband/wavelet transform coding gain, as defined for nonorthogonal wavelet transforms. Optimal LP wavelet filters are given for low levels of encoder complexity, as well as their corresponding integer approximations, to allow for applications limited to using integer arithmetic. These optimal LP filters yield larger coding gains than orthogonal filters with an equivalent complexity. The parameterizations described in this article can be used for the optimization of any other appropriate objective function.

Majani, E.↗
NASA NTRS2008

JPEG 2000 Encoding with Perceptual Distortion Control

An alternative approach has been devised for encoding image data in compliance with JPEG 2000, the most recent still-image data-compression standard of the Joint Photographic Experts Group. Heretofore, JPEG 2000 encoding has been implemented by several related schemes classified as rate-based distortion-minimization encoding. In each of these schemes, the end user specifies a desired bit rate and the encoding algorithm strives to attain that rate while minimizing a mean squared error (MSE). While rate-based distortion minimization is appropriate for transmitting data over a limited-bandwidth channel, it is not the best approach for applications in which the perceptual quality of reconstructed images is a major consideration. A better approach for such applications is the present alternative one, denoted perceptual distortion control, in which the encoding algorithm strives to compress data to the lowest bit rate that yields at least a specified level of perceptual image quality. Some additional background information on JPEG 2000 is prerequisite to a meaningful summary of JPEG encoding with perceptual distortion control. The JPEG 2000 encoding process includes two subprocesses known as tier-1 and tier-2 coding. In order to minimize the MSE for the desired bit rate, a rate-distortion- optimization subprocess is introduced between the tier-1 and tier-2 subprocesses. In tier-1 coding, each coding block is independently bit-plane coded from the most-significant-bit (MSB) plane to the least-significant-bit (LSB) plane, using three coding passes (except for the MSB plane, which is coded using only one "clean up" coding pass). For M bit planes, this subprocess involves a total number of (3M - 2) coding passes. An embedded bit stream is then generated for each coding block. Information on the reduction in distortion and the increase in the bit rate associated with each coding pass is collected. This information is then used in a rate-control procedure to determine the contribution of each coding block to the output compressed bit stream.

Watson, Andrew B.↗
NASA NTRS2004

Accumulate-Repeat-Accumulate-Accumulate-Codes

Inspired by recently proposed Accumulate-Repeat-Accumulate (ARA) codes [15], in this paper we propose a channel coding scheme called Accumulate-Repeat-Accumulate-Accumulate (ARAA) codes. These codes can be seen as serial turbo-like codes or as a subclass of Low Density Parity Check (LDPC) codes, and they have a projected graph or protograph representation; this allows for a high-speed iterative decoder implementation using belief propagation. An ARAA code can be viewed as a precoded Repeat-and-Accumulate (RA) code with puncturing in concatenation with another accumulator, where simply an accumulator is chosen as the precoder; thus ARAA codes have a very fast encoder structure. Using density evolution on their associated protographs, we find examples of rate-lJ2 ARAA codes with maximum variable node degree 4 for which a minimum bit-SNR as low as 0.21 dB from the channel capacity limit can be achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA or Irregular RA (IRA) or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore by puncturing the accumulators we can construct families of higher rate ARAA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results show comparable performance with the best-known LDPC codes but with very low error floor even at moderate block sizes.

density evolution↗
NASA NTRS1989

Implementation issues in source coding

An edge preserving image coding scheme which can be operated in both a lossy and a lossless manner was developed. The technique is an extension of the lossless encoding algorithm developed for the Mars observer spectral data. It can also be viewed as a modification of the DPCM algorithm. A packet video simulator was also developed from an existing modified packet network simulator. The coding scheme for this system is a modification of the mixture block coding (MBC) scheme described in the last report. Coding algorithms for packet video were also investigated.

Sayood, Khalid↗
NASA NTRS2006

Protograph LDPC Codes Over Burst Erasure Channels

In this paper we design high rate protograph based LDPC codes suitable for binary erasure channels. To simplify the encoder and decoder implementation for high data rate transmission, the structure of codes are based on protographs and circulants. These LDPC codes can improve data link and network layer protocols in support of communication networks. Two classes of codes were designed. One class is designed for large block sizes with an iterative decoding threshold that approaches capacity of binary erasure channels. The other class is designed for short block sizes based on maximizing minimum stopping set size. For high code rates and short blocks the second class outperforms the first class.

protgraph based codes↗
NASA NTRS1992

Least Reliable Bits Coding (LRBC) for high data rate satellite communications

An analysis and discussion of a bandwidth efficient multi-level/multi-stage block coded modulation technique called Least Reliable Bits Coding (LRBC) is presented. LRBC uses simple multi-level component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Further, soft-decision multi-stage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Using analytical expressions and tight performance bounds it is shown that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of Binary Phase Shift Keying (BPSK). Bit error rates (BER) vs. channel bit energy with Additive White Gaussian Noise (AWGN) are given for a set of LRB Reed-Solomon (RS) encoded 8PSK modulation formats with an ensemble rate of 8/9. All formats exhibit a spectral efficiency of 2.67 = (log2(8))(8/9) information bps/Hz. Bit by bit coded and uncoded error probabilities with soft-decision information are determined. These are traded with with code rate to determine parameters that achieve good performance. The relative simplicity of Galois field algebra vs. the Viterbi algorithm and the availability of high speed commercial Very Large Scale Integration (VLSI) for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

Vanderaar, Mark↗
NASA NTRS1972

Simulation results for the Viterbi decoding algorithm

Concepts involved in determining the performance of coded digital communications systems are introduced. The basic concepts of convolutional encoding and decoding are summarized, and hardware implementations of sequential and maximum likelihood decoders are described briefly. Results of parametric studies of the Viterbi decoding algorithm are summarized. Bit error probability is chosen as the measure of performance and is calculated, by using digital computer simulations, for various encoder and decoder parameters. Results are presented for code rates of one-half and one-third, for constraint lengths of 4 to 8, for both hard-decision and soft-decision bit detectors, and for several important systematic and nonsystematic codes. The effect of decoder block length on bit error rate also is considered, so that a more complete estimate of the relationship between performance and decoder complexity can be made.

Batson, B. H.↗
NASA NTRS1990

A high speed CCSDS encoder for space applications

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Whitaker, S.↗
NASA NTRS2003

Polycystins 1 and 2 mediate mechanosensation in the primary cilium of kidney cells

Several proteins implicated in the pathogenesis of polycystic kidney disease (PKD) localize to cilia. Furthermore, cilia are malformed in mice with PKD with mutations in TgN737Rpw (encoding polaris). It is not known, however, whether ciliary dysfunction occurs or is relevant to cyst formation in PKD. Here, we show that polycystin-1 (PC1) and polycystin-2 (PC2), proteins respectively encoded by Pkd1 and Pkd2, mouse orthologs of genes mutated in human autosomal dominant PKD, co-distribute in the primary cilia of kidney epithelium. Cells isolated from transgenic mice that lack functional PC1 formed cilia but did not increase Ca(2+) influx in response to physiological fluid flow. Blocking antibodies directed against PC2 similarly abolished the flow response in wild-type cells as did inhibitors of the ryanodine receptor, whereas inhibitors of G-proteins, phospholipase C and InsP(3) receptors had no effect. These data suggest that PC1 and PC2 contribute to fluid-flow sensation by the primary cilium in renal epithelium and that they both function in the same mechanotransduction pathway. Loss or dysfunction of PC1 or PC2 may therefore lead to PKD owing to the inability of cells to sense mechanical cues that normally regulate tissue morphogenesis.

Non-NASA Center↗
NASA NTRS2004

Accumulate repeat accumulate codes

In this paper we propose an innovative channel coding scheme called 'Accumulate Repeat Accumulate codes' (ARA). This class of codes can be viewed as serial turbo-like codes, or as a subclass of Low Density Parity Check (LDPC) codes, thus belief propagation can be used for iterative decoding of ARA codes on a graph. The structure of encoder for this class can be viewed as precoded Repeat Accumulate (RA) code or as precoded Irregular Repeat Accumulate (IRA) code, where simply an accumulator is chosen as a precoder. Thus ARA codes have simple, and very fast encoder structure when they representing LDPC codes. Based on density evolution for LDPC codes through some examples for ARA codes, we show that for maximum variable node degree 5 a minimum bit SNR as low as 0.08 dB from channel capacity for rate 1/2 can be achieved as the block size goes to infinity. Thus based on fixed low maximum variable node degree, its threshold outperforms not only the RA and IRA codes but also the best known LDPC codes with the dame maximum node degree. Furthermore by puncturing the accumulators any desired high rate codes close to code rate 1 can be obtained with thresholds that stay close to the channel capacity thresholds uniformly. Iterative decoding simulation results are provided. The ARA codes also have projected graph or protograph representation that allows for high speed decoder implementation.

Low Density Parity Check codes (LDPC)↗