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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,243 records · Page 69
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Spacecraft optical disk recorder memory buffer control

The goal of this project is to develop an Application Specific Integrated Circuit (ASIC) for use in the control electronics of the Spacecraft Optical Disk Recorder (SODR). Specifically, this project is to design an extendable memory buffer controller ASIC for rate matching between a system Input/Output port and the SODR's device interface. The aforementioned goal can be partitioned into the following sub-goals: (1) completion of ASIC design and simulation (on-going via ASEE fellowship); (2) ASIC Fabrication (at ASIC manufacturer); and (3) ASIC Testing (NASA/LaRC, Christopher Newport University).

Hodson, Robert F.↗
NASA NTRS1993

Thin Rechargeable Batteries for CMOS SRAM Memory Protection

New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.

Crouse, Dennis N.↗
NASA NTRS1993

Dynamic programming on a shared-memory multiprocessor

Three new algorithms for solving dynamic programming problems on a shared-memory parallel computer are described. All three algorithms attempt to balance work load, while keeping synchronization cost low. In particular, for a multiprocessor having p processors, an analysis of the best algorithm shows that the arithmetic cost is O(n-cubed/6p) and that the synchronization cost is O(absolute value of log sub C n) if p much less than n, where C = (2p-1)/(2p + 1) and n is the size of the problem. The low synchronization cost is important for machines where synchronization is expensive. Analysis and experiments show that the best algorithm is effective in balancing the work load and producing high efficiency.

Edmonds, Phil↗
NASA NTRS1993

A new parallel-vector finite element analysis software on distributed-memory computers

A new parallel-vector finite element analysis software package MPFEA (Massively Parallel-vector Finite Element Analysis) is developed for large-scale structural analysis on massively parallel computers with distributed-memory. MPFEA is designed for parallel generation and assembly of the global finite element stiffness matrices as well as parallel solution of the simultaneous linear equations, since these are often the major time-consuming parts of a finite element analysis. Block-skyline storage scheme along with vector-unrolling techniques are used to enhance the vector performance. Communications among processors are carried out concurrently with arithmetic operations to reduce the total execution time. Numerical results on the Intel iPSC/860 computers (such as the Intel Gamma with 128 processors and the Intel Touchstone Delta with 512 processors) are presented, including an aircraft structure and some very large truss structures, to demonstrate the efficiency and accuracy of MPFEA.

Qin, Jiangning↗
NASA NTRS1992

Low power SEU immune CMOS memory circuits

The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

Liu, M. N.↗
NASA NTRS1993

Dynamic overset grid communication on distributed memory parallel processors

A parallel distributed memory implementation of intergrid communication for dynamic overset grids is presented. Included are discussions of various options considered during development. Results are presented comparing an Intel iPSC/860 to a single processor Cray Y-MP. Results for grids in relative motion show the iPSC/860 implementation to be faster than the Cray implementation.

Barszcz, Eric↗
NASA NTRS1993

Satiation or availability? Effects of attention, memory, and imagery on the perception of ambiguous figures

The prolonged-inspection technique has been used to demonstrate effects of satiation on the perception of ambiguous figures. We propose that the inspection phase, in which subjects view an unambiguous version of the stimulus prior to observing the ambiguous figure, does not create neural fatigue but rather provides a context in which the alternative percept is apprehended and gains perceptual strength through processes such as imagination or memory. The consequent availability of the alternative organization drives the perceptual phenomena that have been thought to reflect satiation. In Experiment 1, we demonstrated that (1) preexperimental exposure to the target figures and (2) allocation of attention to the inspection figures were both necessary in order to obtain results similar to those predicted by the satiation model. In Experiment 2, we obtained similar results, finding that effects of prior inspection were greater the greater the amount and availability of information regarding the alternative percept during the inspection phase. Subjects who generated visual images of the noninspected alternative during inspection yielded results comparable to those from subjects to whom both versions were presented visually.

Horlitz, Krista L.↗
NASA NTRS1991

Data systems and computer science space data systems: Onboard memory and storage

The topics are presented in viewgraph form and include the following: technical objectives; technology challenges; state-of-the-art assessment; mass storage comparison; SODR drive and system concepts; program description; vertical Bloch line (VBL) device concept; relationship to external programs; and backup charts for memory and storage.

Shull, Tom↗
NASA NTRS1994

Nonvolatile GaAs Random-Access Memory

Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

Katti, Romney R.↗
NASA NTRS1994

Optoelectronic Terminal-Attractor-Based Associative Memory

Report presents theoretical and experimental study of optically and electronically addressable optical implementation of artificial neural network that performs associative recall. Shows by computer simulation that terminal-attractor-based associative memory can have perfect convergence in associative retrieval and increased storage capacity. Spurious states reduced by exploiting terminal attractors.

Liu, Hua-Kuang↗
NASA NTRS1990

SEU hardening of CMOS memory circuit

This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

Whitaker, S.↗
NASA NTRS1991

Performance of defect-tolerant set-associative cache memories

The increased use of on-chip cache memories has led researchers to investigate their performance in the presence of manufacturing defects. Several techniques for yield improvement are discussed and results are presented which indicate that set-associativity may be used to provide defect tolerance as well as improve the cache performance. Tradeoffs between several cache organizations and replacement strategies are investigated and it is shown that token-based replacement may be a suitable alternative to the widely-used LRU strategy.

Frenzel, J. F.↗
NASA NTRS1993

Test results for SEU and SEL immune memory circuits

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Wiseman, D.↗
NASA NTRS1993

An ASIC memory buffer controller for a high speed disk system

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Hodson, Robert F.↗
NASA NTRS1993

A cross-disciplinary response to improve test activities: The corporate memory capitalization in Ariane4 test domain

The Assembly, Integration, Test, and Validation (AIT/AIV) of the Ariane4 Vehicle Equipment Bay was held at Matra Marconi Space (MMS) site of Toulouse for several years. For this activity, incident interpretation necessitates a great deal of different knowledge. When complex faults occur, particularly those appearing during overall control tests, experts of various domains (EGSE, software, on-board equipment) have to join for investigation sessions. Thus, an assistance tool for the identification of faulty equipment will improve the efficiency of diagnosis and the overall productivity of test activities. As a solution, the Aramiihs laboratory proposed considering the opportunity of a knowledge based system intended to assist the tester in diagnosis. This knowledge based system is, in fact, a short-term achievement of a long-term goal which is the capitalization of corporate memory in the Ariane4 test domain. Aramiihs is a research unit where engineers from MMS and researchers from the IRIT-CNRS cooperate on problems concerning new types of man-system interaction.

Vo, Dinh Phuoc↗
NASA NTRS1994

Shared virtual memory and generalized speedup

Generalized speedup is defined as parallel speed over sequential speed. The generalized speedup and its relation with other existing performance metrics, such as traditional speedup, efficiency, scalability, etc., are carefully studied. In terms of the introduced asymptotic speed, it was shown that the difference between the generalized speedup and the traditional speedup lies in the definition of the efficiency of uniprocessor processing, which is a very important issue in shared virtual memory machines. A scientific application was implemented on a KSR-1 parallel computer. Experimental and theoretical results show that the generalized speedup is distinct from the traditional speedup and provides a more reasonable measurement. In the study of different speedups, various causes of superlinear speedup are also presented.

Sun, Xian-He↗
NASA NTRS1993

Spacecraft optical disk recorder memory buffer control

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Hodson, Robert F.↗