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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,243 records · Page 69

Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing

Current, near-term quantum devices have shown great progress in the last several years culminating recently with a demonstration of quantum supremacy. In the medium-term, however, quantum machines will need to transition to greater reliability through error correction, likely through promising techniques like surface codes which are well suited for near-term devices with limited qubit connectivity. We discover quantum memory, particularly resonant cavities with transmon qubits arranged in a 2.5D architecture, can efficiently implement surface codes with substantial hardware savings and performance/fidelity gains. Specifically, we virtualize logical qubits by storing them in layers of qubit memories connected to each transmon. Surprisingly, distributing each logical qubit across many memories has a minimal impact on fault tolerance and results in substantially more efficient operations. Our design permits fast transversal application of CNOT operations between logical qubits sharing the same physical address (same set of cavities) which are 6x faster than standard lattice surgery CNOTs. We develop a novel embedding which saves approximately 10x in transmons with another 2x savings from an additional optimization for compactness. Although qubit virtualization pays a 10x penalty in serialization, advantages in the transversal CNOT and in area efficiency result in fault-tolerance and performance comparable to conventional 2D transmon-only architectures. Our simulations show our system can achieve fault tolerance comparable to conventional two-dimensional grids while saving substantial hardware. Furthermore, our architecture can produce magic states at 1.22x the baseline rate given a fixed number of transmon qubits. Here, this is a critical benchmark for future fault-tolerant quantum computers as magic states are essential and machines will spend the majority of their resources continuously producing them. This architecture substantially reduces the hardware requirements for fault-tolerant quantum computing and puts within reach a proof-of-concept experimental demonstration of around 10 logical qubits, requiring only 11 transmons and 9 attached cavities in total.

quantum computing↗

Design and analysis of CXL performance models for tightly-coupled heterogeneous computing

Truly heterogeneous systems enable partitioned workloads to be mapped to the hardware that nets the best performance. However, current practice requires that inter-device communication between different vendors' hardware use host memory as an intermediary step. To date, there are no widely adopted solutions that allow accelerators to directly transfer data. A new cache-coherent protocol, CXL, aims to facilitate easier, fine-grained sharing between accelerators. In this work we analyze existing methods for designing heterogeneous applications that target GPUs and FPGAs working collaboratively, followed by an exploration to show the benefits of a CXL-enabled system. Specifically, we develop a test application that utilizes both an NVIDIA P100 GPU and a Xilinx U250 FPGA to show current communication limitations. From this application, we capture overall execution time and throughput measurements on the FPGA and GPU. We use these measurements as inputs to novel CXL performance models to show that using CXL caching instead of host memory results in a 1.31X speedup, while a more tightly-coupled pipelined implementation using CXL-enabled hardware would result in a speedup of 1.45X.

Cabrera, Anthony↗

DESTINY

DESTINY is a comprehensive tool for modeling 3D and 2D cache designs using SRAM,embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM), and phase change RAM (PCN). In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g. latency, area or energy-delay product) for agiven memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target, etc. DESTINY has been validated against several cache prototypes. DESTINY is expected to boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers.

Source record↗

Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

97 MATHEMATICS AND COMPUTING↗

Arms Control Opportunities for Inherently Safe and Secure Nuclear Command, Control, and Communications

The Department of Defense Science Board has stated that the United States is "not prepared to defend againsr cyber-attacks and that the military could lose "trust in the information and ability to control U.S. systems and forces [including nuclear forces]." One potential weak spot in cyber-security is storing encryption keys in computer memory. This paper explores the use of hardware devices (so-called Physical Unclonable Functions, or PUFs) to generate, in the nuclear weapon itself, unique encryption keys each time they are needed. Not only do we find that this has the potential to mitigate a number of cyberthreats, but such hardware has the potential to greatly diminish the total uncertainty associated with radiation-based warhead authentication procedures; a procedure many analysts feel will be key to future arms control regimes. After outline the use of PUFs in nuclear command, control, and communications--and indicating some of the areas that still require further research--we discuss their application to arms control and warhead authentication

98 NUCLEAR DISARMAMENT, SAFEGUARDS, AND PHYSICAL P↗

Encode/Decode facility for FORTRAN 4

An ENCODE and DECODE facility, a subroutine added to a FORTRAN 4 library, allows alphanumeric data to be transfered to or from an area in memory rather than to or from external input/output devices. A buffer storage array allows the operations on the data prior to writing.

Cohn, C. E.↗

Multiport semiconductor devices

Device, made of a variety of semiconductors, incorporates three or more terminals. Between at least two terminals, switching action occurs. The other terminal pair performs either another switching function or a control function. This device is useful for computer-logic or memory applications.

Holmstrom, F. R.↗

The question of the possibility of using Associative Computer Devices (ACD) for parallel adaptive discretization of multichannel telemetry information

The method of parallel adaptive discretization of data is considered the most promising and allows the effective compression algorithms to be used for high information-capacity radio telemetry systems. An associative computer device (ACD), i.e., parallel computers based on associative memory units (AMU), are recommended for realization of this method. A detailed discussion of the problems of application of AMU is followed by description of a particular ACD and its recommended use.

Kantor, A. V.↗

Microcontroller for automation application

A microcontroller for automation application is currently being developed. It is basically an 8-bit microcomputer with a 40K byte random access memory/read only memory, and can control a maximum of 12 devices through standard 15-line interface ports.

H. W. Cooper↗

A video event trigger for high frame rate, high resolution video technology

When video replaces film the digitized video data accumulates very rapidly, leading to a difficult and costly data storage problem. One solution exists for cases when the video images represent continuously repetitive 'static scenes' containing negligible activity, occasionally interrupted by short events of interest. Minutes or hours of redundant video frames can be ignored, and not stored, until activity begins. A new, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term or short term changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pretrigger and post-trigger storage techniques are then adaptable for archiving the digital stream from only the significant video images.

Williams, Glenn L.↗

VLSI-based Video Event Triggering for Image Data Compression

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Williams, Glenn L.↗

Nanoelectronics: Opportunities for future space applications

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Frazier, Gary↗

An At-Home Evaluation of a Light Intervention to Mitigate Sleep Inertia Symptoms

Introduction: Sleep inertia symptoms typically occur after waking from nocturnal sleep. Under laboratory settings, light exposure upon waking has been shown to improve alertness, mood, and vigilant attention. We investigated whether a field-deployable light-emitting device would help to improve alertness and working memory in a real-world setting. Methods: Thirty-five participants (18 female; 26.4 ± 6.0 y) completed an at-home, within-subject, randomized crossover study. Participants wore actiwatches during their normal sleep-wake schedule for five nights ahead of the adaptation and experimental nights. On the experimental night, participants performed baseline testing before their self-selected bedtime. Forty-five minutes after bedtime, participants received a phone call and were instructed to perform test bouts while wearing light-emitting glasses with the light either on (light condition) or off (control). A 3-minute descending subtraction task (DST) and the Karolinska Sleepiness Scale (KSS) were performed at +7, +17, +27, and +37 minutes after the call. Participants were then instructed to go back to sleep and were called 45 minutes after lights out to repeat the test bouts in the opposite condition. A series of mixed-effects models were performed with fixed effects of condition, test bout, and their interaction, and a random effect of participant. Condition order, sex, and baseline were included as covariates. Results: There was a significant effect of test bout for DST total responses (χ2 [3] = 17.42; p < .001) and total correct (χ2 [3] = 21.29; p < .001) with improved performance at +27 and +37 minutes compared to +7 minutes. Sex was a significant predictor for KSS (F1,30 = 10.26; p = .003), with females (8.20 ± 0.23) rating higher sleepiness than males (7.10 ± 0.25). There were no other significant effects for DST or KSS outcomes (p > .05). Conclusion: These results suggest that the intervention was not able to improve working memory or alertness under naturalistic at-home settings. Further analysis is needed to determine whether these results are applicable to other cognitive performance domains.

light↗

DESTINY

DESTINY is a comprehensive tool for modeling 3D and 2D cache designs using SRAM,embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM), and phase change RAM (PCN). In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g. latency, area or energy-delay product) for agiven memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target, etc. DESTINY has been validated against several cache prototypes. DESTINY is expected to boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers.

Source record↗

Preparing an Incompressible-Flow Fluid Dynamics Code for Exascale-Class Wind Energy Simulations: Preprint

The US Department of Energy has identified Exascale-Class wind farm simulation tools as critical to wind energy scientific discovery. A primary objective of the Exawind project is to build high-performance, predictive Computational Fluid Dynamics tools that satisfy these modeling needs. GPU accelerators will serve as the computational thoroughbreds of next generation, Exascale-Class, platforms. Here, we report on our efforts for preparing the Exawind unstructured mesh solver, Nalu-Wind, for Exascale-Class machines. For computing at this scale, a simple port of the incompressible-flow algorithms to GPUs is not sufficient. One needs novel algorithms that are application aware, memory efficient, and optimized for latest generation GPU devices to get high-performance. The result of our efforts are unstructured mesh simulations of wind turbines that use 1/6 the compute resources of Summit supercomputer at Oak Ridge National Lab. In particular, we demonstrate a first-of-its-kind, simulation using Algebraic Multigrid solvers on over 4000 GPUs.

algebraic multigrid↗

SU-F-T-505: A Novel Approach for Sparing Critical Organs at Risk for Cancer Patients Undergoing Radiation Oncology Treatments

Purpose: A major goal of an effective radiation treatment plan is to deliver the maximum dose to the tumor while minimizing radiation exposure to the surrounding normal structures. For example, due to the radiation exposure to neighboring critical structures during prostate cancer treatment, a significant increase in cancer risk was observed for the bladder (77%) and the rectum (105%) over the following decade. Consequently, an effective treatment plan necessitates limiting the exposure to such organs which can best be achieved by physically displacing the organ at-risk. The goal of this study is to present a prototype for an organ re-positioner device designed and fabricated to physically move the rectum away from the path of radiation beam during external beam and brachytherapy treatments. This device affords patient comfort and provides a fully controlled motion to safely relocate the rectum during treatment. Methods: The NiTi shape memory alloy was designed and optimized for manufacturing a rectal re-positioner device through cooling and heating the core alloy for its shaping. This has been achieved through a prototyped custom designed electronic circuit in order to induce the reversible austenitic transformation and was tested rigorously to ensure the integrity of the actuated motion in displacement of the target anatomy. Results: The desirable NiTi shape-setting was configured for easy insertion and based on anatomical constraint. When the final prototype was evaluated, accuracy and precision of the maximum displacement and temperature changes revealed that the device could safely be used within the target anatomy. Conclusion: The organ re-positioner device is a promising tool that can be implemented in clinical setting. It provides a controlled and safe displacement of the delicate organ(s) at risk. The location of the organ being treated could also be identified using conventional onboard imaging devices or MV imaging available on-board most modern clinical accelerators.

60 APPLIED LIFE SCIENCES↗

On a photon-counting array using the Fairchild CCD-201

The evaluation of certain performance parameters of the Fairchild CCD 201 and the proposed method of operation of an electron bombarded charge coupled device are described. Work in progress on the evaluation of the parameters relevant to remote, low noise operation is reported. These tests have been conducted using light input. The video data from the CCD are amplified, digitized, stored in a minicomputer memory, and then recorded on magnetic tape for analyzing. The device will be used in an array of sensors in the aperture plane of a telescope to discriminate between photoelectron events, and in the focal plane operating at single photoelectron sensitivity at a minimum of blooming and lag.

Currie, D. G.↗

Synchronization for CXL Based Memory

Compute Express Link (CXL) is an important emerging standard for disaggregated memory. While this standard provisions coherency across numerous hosts and devices, implementing hardware support for type three devices is challenging. In this work, we look at the overhead of software synchronization and using software-based coherency. Moreover, we discuss the limits of software-based coherency in fully expressing modern synchronization techniques for a CXL-based disaggregate memory system. We demonstrate our approach using a CXL hardware prototype and running a version of the famous Peterson Lock (enhanced to run with more than two threads). We analyze its performance and share how more advanced synchronization techniques might interact with software-based coherence CXL hardware and program execution models.

High Performance Computing (HPC)↗